1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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80TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
81{
82 if (status == RangeChange)
83 return;
84
85 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
86}
87
88TimingSimpleCPU::TimingSimpleCPU(Params *p)
89 : BaseSimpleCPU(p), icachePort(this), dcachePort(this)
90{
91 _status = Idle;
92 ifetch_pkt = dcache_pkt = NULL;
93 drainEvent = NULL;
94 fetchEvent = NULL;
95 changeState(SimObject::Running);
96}
97

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457 } else {
458 // non-memory instruction: execute completely now
459 Fault fault = curStaticInst->execute(this, traceData);
460 postExecute();
461 advanceInst(fault);
462 }
463}
464
465
466bool
467TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
468{
469 cpu->completeIfetch(pkt);
470 return true;
471}
472
473void
474TimingSimpleCPU::IcachePort::recvRetry()
475{
476 // we shouldn't get a retry unless we have a packet that we're
477 // waiting to transmit

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518 DPRINTF(Config, "Done draining\n");
519 changeState(SimObject::Drained);
520 drainEvent->process();
521}
522
523bool
524TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
525{
526 cpu->completeDataAccess(pkt);
527 return true;
528}
529
530void
531TimingSimpleCPU::DcachePort::recvRetry()
532{
533 // we shouldn't get a retry unless we have a packet that we're
534 // waiting to transmit
535 assert(cpu->dcache_pkt != NULL);
536 assert(cpu->_status == DcacheRetry);
537 Packet *tmp = cpu->dcache_pkt;
538 if (sendTiming(tmp)) {

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