1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 19 unchanged lines hidden (view full) ---

28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/utility.hh"
32#include "cpu/exetrace.hh"
33#include "cpu/simple/timing.hh"
34#include "mem/packet_impl.hh"
35#include "sim/builder.hh"
36
37using namespace std;
38using namespace TheISA;
39
40Port *
41TimingSimpleCPU::getPort(const std::string &if_name, int idx)
42{
43 if (if_name == "dcache_port")

--- 42 unchanged lines hidden (view full) ---

86
87TimingSimpleCPU::TimingSimpleCPU(Params *p)
88 : BaseSimpleCPU(p), icachePort(this), dcachePort(this)
89{
90 _status = Idle;
91 ifetch_pkt = dcache_pkt = NULL;
92 drainEvent = NULL;
93 fetchEvent = NULL;
94 state = SimObject::Timing;
95}
96
97
98TimingSimpleCPU::~TimingSimpleCPU()
99{
100}
101
102void

--- 5 unchanged lines hidden (view full) ---

108
109void
110TimingSimpleCPU::unserialize(Checkpoint *cp, const string &section)
111{
112 UNSERIALIZE_ENUM(_status);
113 BaseSimpleCPU::unserialize(cp, section);
114}
115
116bool
117TimingSimpleCPU::drain(Event *drain_event)
118{
119 // TimingSimpleCPU is ready to drain if it's not waiting for
120 // an access to complete.
121 if (status() == Idle || status() == Running || status() == SwitchedOut) {
122 changeState(SimObject::DrainedTiming);
123 return true;
124 } else {
125 changeState(SimObject::Draining);
126 drainEvent = drain_event;
127 return false;
128 }
129}
130
131void
132TimingSimpleCPU::resume()
133{
134 if (_status != SwitchedOut && _status != Idle) {
135 // Delete the old event if it existed.
136 if (fetchEvent) {
137 assert(!fetchEvent->scheduled());
138 delete fetchEvent;
139 }
140
141 fetchEvent =
142 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
143 fetchEvent->schedule(curTick);
144 }
145}
146
147void
148TimingSimpleCPU::setMemoryMode(State new_mode)
149{
150 assert(new_mode == SimObject::Timing);
151}
152
153void
154TimingSimpleCPU::switchOut()
155{
156 assert(status() == Running || status() == Idle);
157 _status = SwitchedOut;
158

--- 350 unchanged lines hidden (view full) ---

509 advanceInst(fault);
510}
511
512
513void
514TimingSimpleCPU::completeDrain()
515{
516 DPRINTF(Config, "Done draining\n");
517 changeState(SimObject::DrainedTiming);
518 drainEvent->process();
519}
520
521bool
522TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
523{
524 cpu->completeDataAccess(pkt);
525 return true;

--- 20 unchanged lines hidden (view full) ---

546//
547BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
548
549 Param<Counter> max_insts_any_thread;
550 Param<Counter> max_insts_all_threads;
551 Param<Counter> max_loads_any_thread;
552 Param<Counter> max_loads_all_threads;
553 SimObjectParam<MemObject *> mem;
554
555#if FULL_SYSTEM
556 SimObjectParam<AlphaITB *> itb;
557 SimObjectParam<AlphaDTB *> dtb;
558 SimObjectParam<System *> system;
559 Param<int> cpu_id;
560 Param<Tick> profile;
561#else
562 SimObjectParam<Process *> workload;
563#endif // FULL_SYSTEM
564
565 Param<int> clock;
566

--- 11 unchanged lines hidden (view full) ---

578 "terminate when any thread reaches this inst count"),
579 INIT_PARAM(max_insts_all_threads,
580 "terminate when all threads have reached this inst count"),
581 INIT_PARAM(max_loads_any_thread,
582 "terminate when any thread reaches this load count"),
583 INIT_PARAM(max_loads_all_threads,
584 "terminate when all threads have reached this load count"),
585 INIT_PARAM(mem, "memory"),
586
587#if FULL_SYSTEM
588 INIT_PARAM(itb, "Instruction TLB"),
589 INIT_PARAM(dtb, "Data TLB"),
590 INIT_PARAM(system, "system object"),
591 INIT_PARAM(cpu_id, "processor ID"),
592 INIT_PARAM(profile, ""),
593#else
594 INIT_PARAM(workload, "processes to run"),
595#endif // FULL_SYSTEM
596
597 INIT_PARAM(clock, "clock speed"),
598 INIT_PARAM(defer_registration, "defer system registration (for sampling)"),

--- 14 unchanged lines hidden (view full) ---

613 params->max_insts_all_threads = max_insts_all_threads;
614 params->max_loads_any_thread = max_loads_any_thread;
615 params->max_loads_all_threads = max_loads_all_threads;
616 params->deferRegistration = defer_registration;
617 params->clock = clock;
618 params->functionTrace = function_trace;
619 params->functionTraceStart = function_trace_start;
620 params->mem = mem;
621
622#if FULL_SYSTEM
623 params->itb = itb;
624 params->dtb = dtb;
625 params->system = system;
626 params->cpu_id = cpu_id;
627 params->profile = profile;
628#else
629 params->process = workload;
630#endif
631
632 TimingSimpleCPU *cpu = new TimingSimpleCPU(params);
633 return cpu;
634}
635
636REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU)
637