1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
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447 advanceInst(fault);
448 }
449}
450
451
452bool
453TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
454{
455 if (cpu->_status == DcacheWaitResponse)
456 cpu->completeDataAccess(pkt);
457 else if (cpu->_status == IcacheWaitResponse)
458 cpu->completeIfetch(pkt);
459 else
460 assert("OOPS" && 0);
461 return true;
462}
463
464void
465TimingSimpleCPU::IcachePort::recvRetry()
466{
467 // we shouldn't get a retry unless we have a packet that we're
468 // waiting to transmit
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2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
--- 438 unchanged lines hidden (view full) ---
447 advanceInst(fault);
448 }
449}
450
451
452bool
453TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
454{
455 if (cpu->_status == DcacheWaitResponse)
456 cpu->completeDataAccess(pkt);
457 else if (cpu->_status == IcacheWaitResponse)
458 cpu->completeIfetch(pkt);
459 else
460 assert("OOPS" && 0);
461 return true;
462}
463
464void
465TimingSimpleCPU::IcachePort::recvRetry()
466{
467 // we shouldn't get a retry unless we have a packet that we're
468 // waiting to transmit
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