1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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83 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
84}
85
86TimingSimpleCPU::TimingSimpleCPU(Params *p)
87 : BaseSimpleCPU(p), icachePort(this), dcachePort(this)
88{
89 _status = Idle;
90 ifetch_pkt = dcache_pkt = NULL;
91}
92
93
94TimingSimpleCPU::~TimingSimpleCPU()
95{
96}
97
98void
99TimingSimpleCPU::serialize(ostream &os)
100{
101 BaseSimpleCPU::serialize(os);
102 SERIALIZE_ENUM(_status);
103}
104
105void
106TimingSimpleCPU::unserialize(Checkpoint *cp, const string &section)
107{
108 BaseSimpleCPU::unserialize(cp, section);
109 UNSERIALIZE_ENUM(_status);
110}
111
112void
113TimingSimpleCPU::switchOut(Sampler *s)
114{
115 sampler = s;
116 if (status() == Running) {
117 _status = SwitchedOut;
118 }
119 sampler->signalSwitched();
120}
121
122
123void
124TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
125{
126 BaseCPU::takeOverFrom(oldCPU);
127
128 // if any of this CPU's ThreadContexts are active, mark the CPU as
129 // running and schedule its tick event.
130 for (int i = 0; i < threadContexts.size(); ++i) {
131 ThreadContext *tc = threadContexts[i];

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378
379void
380TimingSimpleCPU::completeIfetch(Packet *pkt)
381{
382 // received a response from the icache: execute the received
383 // instruction
384 assert(pkt->result == Packet::Success);
385 assert(_status == IcacheWaitResponse);
386 _status = Running;
387
388 delete pkt->req;
389 delete pkt;
390
391 preExecute();
392 if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
393 // load or store: just send to dcache
394 Fault fault = curStaticInst->initiateAcc(this, traceData);
395 if (fault == NoFault) {
396 // successfully initiated access: instruction will
397 // complete in dcache response callback
398 assert(_status == DcacheWaitResponse);

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435TimingSimpleCPU::completeDataAccess(Packet *pkt)
436{
437 // received a response from the dcache: complete the load or store
438 // instruction
439 assert(pkt->result == Packet::Success);
440 assert(_status == DcacheWaitResponse);
441 _status = Running;
442
443 Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
444
445 delete pkt->req;
446 delete pkt;
447
448 postExecute();
449 advanceInst(fault);
450}
451
452
453
454bool
455TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
456{
457 cpu->completeDataAccess(pkt);
458 return true;
459}
460

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