1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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167 _status = Idle;
168}
169
170
171template <class T>
172Fault
173TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
174{
175 Request *data_read_req = new Request(true);
176
177 data_read_req->setVaddr(addr);
178 data_read_req->setSize(sizeof(T));
179 data_read_req->setFlags(flags);
180 data_read_req->setTime(curTick);
181
182 if (traceData) {
183 traceData->setAddr(data_read_req->getVaddr());
184 }
185
186 // translate to physical address
187 Fault fault = cpuXC->translateDataReadReq(data_read_req);
188

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250 return read(addr, (uint32_t&)data, flags);
251}
252
253
254template <class T>
255Fault
256TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
257{
258 Request *data_write_req = new Request(true);
259 data_write_req->setVaddr(addr);
260 data_write_req->setTime(curTick);
261 data_write_req->setSize(sizeof(T));
262 data_write_req->setFlags(flags);
263
264 // translate to physical address
265 Fault fault = cpuXC->translateDataWriteReq(data_write_req);
266 // Now do the access.
267 if (fault == NoFault) {
268 Packet *data_write_pkt =
269 new Packet(data_write_req, Packet::WriteReq, Packet::Broadcast);
270 data_write_pkt->allocate();

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335}
336
337
338void
339TimingSimpleCPU::fetch()
340{
341 checkForInterrupts();
342
343 Request *ifetch_req = new Request(true);
344 ifetch_req->setSize(sizeof(MachInst));
345 Fault fault = setupFetchRequest(ifetch_req);
346
347 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
348 ifetch_pkt->dataStatic(&inst);
349
350 if (fault == NoFault) {
351 if (!icachePort.sendTiming(ifetch_pkt)) {
352 // Need to wait for retry

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