1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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153
154
155void
156TimingSimpleCPU::suspendContext(int thread_num)
157{
158 assert(thread_num == 0);
159 assert(cpuXC);
160
161 panic("TimingSimpleCPU::suspendContext not implemented");
162
163 assert(_status == Running);
164
165 notIdleFraction--;
166 _status = Idle;
167}
168
169
170template <class T>
171Fault
172TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)

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352 _status = IcacheRetry;
353 } else {
354 // Need to wait for cache to respond
355 _status = IcacheWaitResponse;
356 // ownership of packet transferred to memory system
357 ifetch_pkt = NULL;
358 }
359 } else {
360 panic("TimingSimpleCPU fetch fault handling not implemented");
361 }
362}
363
364
365void
366TimingSimpleCPU::completeInst(Fault fault)
367{
368 postExecute();
369
370 if (traceData) {
371 traceData->finalize();
372 }
373
374 advancePC(fault);
375
376 if (_status == Running) {
377 // kick off fetch of next instruction... callback from icache
378 // response will cause that instruction to be executed,
379 // keeping the CPU running.
380 fetch();
381 }
382}
383
384
385void
386TimingSimpleCPU::completeIfetch()
387{
388 // received a response from the icache: execute the received
389 // instruction
390 assert(_status == IcacheWaitResponse);
391 _status = Running;
392 preExecute();
393 if (curStaticInst->isMemRef()) {
394 // load or store: just send to dcache
395 Fault fault = curStaticInst->initiateAcc(this, traceData);
396 assert(fault == NoFault);
397 assert(_status == DcacheWaitResponse);
398 // instruction will complete in dcache response callback
399 } else {
400 // non-memory instruction: execute completely now
401 Fault fault = curStaticInst->execute(this, traceData);
402 completeInst(fault);
403 }
404}
405
406
407bool
408TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
409{
410 cpu->completeIfetch();
411 return true;
412}
413
414Packet *
415TimingSimpleCPU::IcachePort::recvRetry()
416{
417 // we shouldn't get a retry unless we have a packet that we're
418 // waiting to transmit

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430 // received a response from the dcache: complete the load or store
431 // instruction
432 assert(pkt->result == Packet::Success);
433 assert(_status == DcacheWaitResponse);
434 _status = Running;
435
436 Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
437
438 completeInst(fault);
439}
440
441
442
443bool
444TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
445{
446 cpu->completeDataAccess(pkt);

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