1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 */
42
43#include "arch/locked_mem.hh"
44#include "arch/mmapped_ipr.hh"
45#include "arch/utility.hh"
46#include "base/bigint.hh"
47#include "config/the_isa.hh"
48#include "cpu/simple/timing.hh"
49#include "cpu/exetrace.hh"
50#include "debug/Config.hh"
51#include "debug/ExecFaulting.hh"
52#include "debug/SimpleCPU.hh"
53#include "mem/packet.hh"
54#include "mem/packet_access.hh"
55#include "params/TimingSimpleCPU.hh"
56#include "sim/faults.hh"
57#include "sim/full_system.hh"
58#include "sim/system.hh"
59
60using namespace std;
61using namespace TheISA;
62
63void
64TimingSimpleCPU::init()
65{
66 BaseCPU::init();
67
68 // Initialise the ThreadContext's memory proxies
69 tcBase()->initMemProxies(tcBase());
70
71 if (FullSystem) {
72 for (int i = 0; i < threadContexts.size(); ++i) {
73 ThreadContext *tc = threadContexts[i];
74 // initialize CPU, including PC
75 TheISA::initCPU(tc, _cpuId);
76 }
77 }
78}
79
80void
81TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
82{
83 pkt = _pkt;
84 cpu->schedule(this, t);
85}
86
87TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
88 : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this),
89 dcachePort(this), fetchEvent(this)
90{
91 _status = Idle;
92
93 ifetch_pkt = dcache_pkt = NULL;
94 drainEvent = NULL;
95 previousTick = 0;
96 changeState(SimObject::Running);
97 system->totalNumInsts = 0;
98}
99
100
101TimingSimpleCPU::~TimingSimpleCPU()
102{
103}
104
105void
106TimingSimpleCPU::serialize(ostream &os)
107{
108 SimObject::State so_state = SimObject::getState();
109 SERIALIZE_ENUM(so_state);
110 BaseSimpleCPU::serialize(os);
111}
112
113void
114TimingSimpleCPU::unserialize(Checkpoint *cp, const string &section)
115{
116 SimObject::State so_state;
117 UNSERIALIZE_ENUM(so_state);
118 BaseSimpleCPU::unserialize(cp, section);
119}
120
121unsigned int
122TimingSimpleCPU::drain(Event *drain_event)
123{
124 // TimingSimpleCPU is ready to drain if it's not waiting for
125 // an access to complete.
126 if (_status == Idle || _status == Running || _status == SwitchedOut) {
127 changeState(SimObject::Drained);
128 return 0;
129 } else {
130 changeState(SimObject::Draining);
131 drainEvent = drain_event;
132 return 1;
133 }
134}
135
136void
137TimingSimpleCPU::resume()
138{
139 DPRINTF(SimpleCPU, "Resume\n");
140 if (_status != SwitchedOut && _status != Idle) {
141 assert(system->getMemoryMode() == Enums::timing);
142
143 if (fetchEvent.scheduled())
144 deschedule(fetchEvent);
145
146 schedule(fetchEvent, nextCycle());
147 }
148
149 changeState(SimObject::Running);
150}
151
152void
153TimingSimpleCPU::switchOut()
154{
155 assert(_status == Running || _status == Idle);
156 _status = SwitchedOut;
157 numCycles += tickToCycles(curTick() - previousTick);
158
159 // If we've been scheduled to resume but are then told to switch out,
160 // we'll need to cancel it.
161 if (fetchEvent.scheduled())
162 deschedule(fetchEvent);
163}
164
165
166void
167TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
168{
169 BaseCPU::takeOverFrom(oldCPU);
170
171 // if any of this CPU's ThreadContexts are active, mark the CPU as
172 // running and schedule its tick event.
173 for (int i = 0; i < threadContexts.size(); ++i) {
174 ThreadContext *tc = threadContexts[i];
175 if (tc->status() == ThreadContext::Active && _status != Running) {
176 _status = Running;
177 break;
178 }
179 }
180
181 if (_status != Running) {
182 _status = Idle;
183 }
184 assert(threadContexts.size() == 1);
185 previousTick = curTick();
186}
187
188
189void
190TimingSimpleCPU::activateContext(ThreadID thread_num, int delay)
191{
192 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
193
194 assert(thread_num == 0);
195 assert(thread);
196
197 assert(_status == Idle);
198
199 notIdleFraction++;
200 _status = Running;
201
202 // kick things off by initiating the fetch of the next instruction
203 schedule(fetchEvent, nextCycle(curTick() + ticks(delay)));
204}
205
206
207void
208TimingSimpleCPU::suspendContext(ThreadID thread_num)
209{
210 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
211
212 assert(thread_num == 0);
213 assert(thread);
214
215 if (_status == Idle)
216 return;
217
218 assert(_status == Running);
219
220 // just change status to Idle... if status != Running,
221 // completeInst() will not initiate fetch of next instruction.
222
223 notIdleFraction--;
224 _status = Idle;
225}
226
227bool
228TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
229{
230 RequestPtr req = pkt->req;
231 if (req->isMmappedIpr()) {
232 Tick delay;
233 delay = TheISA::handleIprRead(thread->getTC(), pkt);
234 new IprEvent(pkt, this, nextCycle(curTick() + delay));
235 _status = DcacheWaitResponse;
236 dcache_pkt = NULL;
237 } else if (!dcachePort.sendTiming(pkt)) {
238 _status = DcacheRetry;
239 dcache_pkt = pkt;
240 } else {
241 _status = DcacheWaitResponse;
242 // memory system takes ownership of packet
243 dcache_pkt = NULL;
244 }
245 return dcache_pkt == NULL;
246}
247
248void
249TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res,
250 bool read)
251{
252 PacketPtr pkt;
253 buildPacket(pkt, req, read);
254 pkt->dataDynamicArray<uint8_t>(data);
255 if (req->getFlags().isSet(Request::NO_ACCESS)) {
256 assert(!dcache_pkt);
257 pkt->makeResponse();
258 completeDataAccess(pkt);
259 } else if (read) {
260 handleReadPacket(pkt);
261 } else {
262 bool do_access = true; // flag to suppress cache access
263
264 if (req->isLLSC()) {
265 do_access = TheISA::handleLockedWrite(thread, req);
266 } else if (req->isCondSwap()) {
267 assert(res);
268 req->setExtraData(*res);
269 }
270
271 if (do_access) {
272 dcache_pkt = pkt;
273 handleWritePacket();
274 } else {
275 _status = DcacheWaitResponse;
276 completeDataAccess(pkt);
277 }
278 }
279}
280
281void
282TimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2,
283 RequestPtr req, uint8_t *data, bool read)
284{
285 PacketPtr pkt1, pkt2;
286 buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read);
287 if (req->getFlags().isSet(Request::NO_ACCESS)) {
288 assert(!dcache_pkt);
289 pkt1->makeResponse();
290 completeDataAccess(pkt1);
291 } else if (read) {
292 SplitFragmentSenderState * send_state =
293 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
294 if (handleReadPacket(pkt1)) {
295 send_state->clearFromParent();
296 send_state = dynamic_cast<SplitFragmentSenderState *>(
297 pkt2->senderState);
298 if (handleReadPacket(pkt2)) {
299 send_state->clearFromParent();
300 }
301 }
302 } else {
303 dcache_pkt = pkt1;
304 SplitFragmentSenderState * send_state =
305 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
306 if (handleWritePacket()) {
307 send_state->clearFromParent();
308 dcache_pkt = pkt2;
309 send_state = dynamic_cast<SplitFragmentSenderState *>(
310 pkt2->senderState);
311 if (handleWritePacket()) {
312 send_state->clearFromParent();
313 }
314 }
315 }
316}
317
318void
319TimingSimpleCPU::translationFault(Fault fault)
320{
321 // fault may be NoFault in cases where a fault is suppressed,
322 // for instance prefetches.
323 numCycles += tickToCycles(curTick() - previousTick);
324 previousTick = curTick();
325
326 if (traceData) {
327 // Since there was a fault, we shouldn't trace this instruction.
328 delete traceData;
329 traceData = NULL;
330 }
331
332 postExecute();
333
334 if (getState() == SimObject::Draining) {
335 advancePC(fault);
336 completeDrain();
337 } else {
338 advanceInst(fault);
339 }
340}
341
342void
343TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read)
344{
345 MemCmd cmd;
346 if (read) {
347 cmd = MemCmd::ReadReq;
348 if (req->isLLSC())
349 cmd = MemCmd::LoadLockedReq;
350 } else {
351 cmd = MemCmd::WriteReq;
352 if (req->isLLSC()) {
353 cmd = MemCmd::StoreCondReq;
354 } else if (req->isSwap()) {
355 cmd = MemCmd::SwapReq;
356 }
357 }
358 pkt = new Packet(req, cmd, Packet::Broadcast);
359}
360
361void
362TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
363 RequestPtr req1, RequestPtr req2, RequestPtr req,
364 uint8_t *data, bool read)
365{
366 pkt1 = pkt2 = NULL;
367
368 assert(!req1->isMmappedIpr() && !req2->isMmappedIpr());
369
370 if (req->getFlags().isSet(Request::NO_ACCESS)) {
371 buildPacket(pkt1, req, read);
372 return;
373 }
374
375 buildPacket(pkt1, req1, read);
376 buildPacket(pkt2, req2, read);
377
378 req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags(), dataMasterId());
379 PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(),
380 Packet::Broadcast);
381
382 pkt->dataDynamicArray<uint8_t>(data);
383 pkt1->dataStatic<uint8_t>(data);
384 pkt2->dataStatic<uint8_t>(data + req1->getSize());
385
386 SplitMainSenderState * main_send_state = new SplitMainSenderState;
387 pkt->senderState = main_send_state;
388 main_send_state->fragments[0] = pkt1;
389 main_send_state->fragments[1] = pkt2;
390 main_send_state->outstanding = 2;
391 pkt1->senderState = new SplitFragmentSenderState(pkt, 0);
392 pkt2->senderState = new SplitFragmentSenderState(pkt, 1);
393}
394
395Fault
396TimingSimpleCPU::readMem(Addr addr, uint8_t *data,
397 unsigned size, unsigned flags)
398{
399 Fault fault;
400 const int asid = 0;
401 const ThreadID tid = 0;
402 const Addr pc = thread->instAddr();
403 unsigned block_size = dcachePort.peerBlockSize();
404 BaseTLB::Mode mode = BaseTLB::Read;
405
406 if (traceData) {
407 traceData->setAddr(addr);
408 }
409
410 RequestPtr req = new Request(asid, addr, size,
411 flags, dataMasterId(), pc, _cpuId, tid);
412
413 Addr split_addr = roundDown(addr + size - 1, block_size);
414 assert(split_addr <= addr || split_addr - addr < block_size);
415
416 _status = DTBWaitResponse;
417 if (split_addr > addr) {
418 RequestPtr req1, req2;
419 assert(!req->isLLSC() && !req->isSwap());
420 req->splitOnVaddr(split_addr, req1, req2);
421
422 WholeTranslationState *state =
423 new WholeTranslationState(req, req1, req2, new uint8_t[size],
424 NULL, mode);
425 DataTranslation<TimingSimpleCPU *> *trans1 =
426 new DataTranslation<TimingSimpleCPU *>(this, state, 0);
427 DataTranslation<TimingSimpleCPU *> *trans2 =
428 new DataTranslation<TimingSimpleCPU *>(this, state, 1);
429
430 thread->dtb->translateTiming(req1, tc, trans1, mode);
431 thread->dtb->translateTiming(req2, tc, trans2, mode);
432 } else {
433 WholeTranslationState *state =
434 new WholeTranslationState(req, new uint8_t[size], NULL, mode);
435 DataTranslation<TimingSimpleCPU *> *translation
436 = new DataTranslation<TimingSimpleCPU *>(this, state);
437 thread->dtb->translateTiming(req, tc, translation, mode);
438 }
439
440 return NoFault;
441}
442
443bool
444TimingSimpleCPU::handleWritePacket()
445{
446 RequestPtr req = dcache_pkt->req;
447 if (req->isMmappedIpr()) {
448 Tick delay;
449 delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
450 new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay));
451 _status = DcacheWaitResponse;
452 dcache_pkt = NULL;
453 } else if (!dcachePort.sendTiming(dcache_pkt)) {
454 _status = DcacheRetry;
455 } else {
456 _status = DcacheWaitResponse;
457 // memory system takes ownership of packet
458 dcache_pkt = NULL;
459 }
460 return dcache_pkt == NULL;
461}
462
463Fault
464TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
465 Addr addr, unsigned flags, uint64_t *res)
466{
467 uint8_t *newData = new uint8_t[size];
468 memcpy(newData, data, size);
469
470 const int asid = 0;
471 const ThreadID tid = 0;
472 const Addr pc = thread->instAddr();
473 unsigned block_size = dcachePort.peerBlockSize();
474 BaseTLB::Mode mode = BaseTLB::Write;
475
476 if (traceData) {
477 traceData->setAddr(addr);
478 }
479
480 RequestPtr req = new Request(asid, addr, size,
481 flags, dataMasterId(), pc, _cpuId, tid);
482
483 Addr split_addr = roundDown(addr + size - 1, block_size);
484 assert(split_addr <= addr || split_addr - addr < block_size);
485
486 _status = DTBWaitResponse;
487 if (split_addr > addr) {
488 RequestPtr req1, req2;
489 assert(!req->isLLSC() && !req->isSwap());
490 req->splitOnVaddr(split_addr, req1, req2);
491
492 WholeTranslationState *state =
493 new WholeTranslationState(req, req1, req2, newData, res, mode);
494 DataTranslation<TimingSimpleCPU *> *trans1 =
495 new DataTranslation<TimingSimpleCPU *>(this, state, 0);
496 DataTranslation<TimingSimpleCPU *> *trans2 =
497 new DataTranslation<TimingSimpleCPU *>(this, state, 1);
498
499 thread->dtb->translateTiming(req1, tc, trans1, mode);
500 thread->dtb->translateTiming(req2, tc, trans2, mode);
501 } else {
502 WholeTranslationState *state =
503 new WholeTranslationState(req, newData, res, mode);
504 DataTranslation<TimingSimpleCPU *> *translation =
505 new DataTranslation<TimingSimpleCPU *>(this, state);
506 thread->dtb->translateTiming(req, tc, translation, mode);
507 }
508
509 // Translation faults will be returned via finishTranslation()
510 return NoFault;
511}
512
513
514void
515TimingSimpleCPU::finishTranslation(WholeTranslationState *state)
516{
517 _status = Running;
518
519 if (state->getFault() != NoFault) {
520 if (state->isPrefetch()) {
521 state->setNoFault();
522 }
523 delete [] state->data;
524 state->deleteReqs();
525 translationFault(state->getFault());
526 } else {
527 if (!state->isSplit) {
528 sendData(state->mainReq, state->data, state->res,
529 state->mode == BaseTLB::Read);
530 } else {
531 sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq,
532 state->data, state->mode == BaseTLB::Read);
533 }
534 }
535
536 delete state;
537}
538
539
540void
541TimingSimpleCPU::fetch()
542{
543 DPRINTF(SimpleCPU, "Fetch\n");
544
545 if (!curStaticInst || !curStaticInst->isDelayedCommit())
546 checkForInterrupts();
547
548 checkPcEventQueue();
549
550 // We must have just got suspended by a PC event
551 if (_status == Idle)
552 return;
553
554 TheISA::PCState pcState = thread->pcState();
555 bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst;
556
557 if (needToFetch) {
558 _status = Running;
559 Request *ifetch_req = new Request();
560 ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
561 setupFetchRequest(ifetch_req);
562 DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr());
563 thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation,
564 BaseTLB::Execute);
565 } else {
566 _status = IcacheWaitResponse;
567 completeIfetch(NULL);
568
569 numCycles += tickToCycles(curTick() - previousTick);
570 previousTick = curTick();
571 }
572}
573
574
575void
576TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
577{
578 if (fault == NoFault) {
579 DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n",
580 req->getVaddr(), req->getPaddr());
581 ifetch_pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
582 ifetch_pkt->dataStatic(&inst);
583 DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr());
584
585 if (!icachePort.sendTiming(ifetch_pkt)) {
586 // Need to wait for retry
587 _status = IcacheRetry;
588 } else {
589 // Need to wait for cache to respond
590 _status = IcacheWaitResponse;
591 // ownership of packet transferred to memory system
592 ifetch_pkt = NULL;
593 }
594 } else {
595 DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr());
596 delete req;
597 // fetch fault: advance directly to next instruction (fault handler)
598 _status = Running;
599 advanceInst(fault);
600 }
601
602 numCycles += tickToCycles(curTick() - previousTick);
603 previousTick = curTick();
604}
605
606
607void
608TimingSimpleCPU::advanceInst(Fault fault)
609{
610
611 if (_status == Faulting)
612 return;
613
614 if (fault != NoFault) {
615 advancePC(fault);
616 DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n");
617 reschedule(fetchEvent, nextCycle(), true);
618 _status = Faulting;
619 return;
620 }
621
622
623 if (!stayAtPC)
624 advancePC(fault);
625
626 if (_status == Running) {
627 // kick off fetch of next instruction... callback from icache
628 // response will cause that instruction to be executed,
629 // keeping the CPU running.
630 fetch();
631 }
632}
633
634
635void
636TimingSimpleCPU::completeIfetch(PacketPtr pkt)
637{
638 DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ?
639 pkt->getAddr() : 0);
640
641 // received a response from the icache: execute the received
642 // instruction
643
644 assert(!pkt || !pkt->isError());
645 assert(_status == IcacheWaitResponse);
646
647 _status = Running;
648
649 numCycles += tickToCycles(curTick() - previousTick);
650 previousTick = curTick();
651
652 if (getState() == SimObject::Draining) {
653 if (pkt) {
654 delete pkt->req;
655 delete pkt;
656 }
657
658 completeDrain();
659 return;
660 }
661
662 preExecute();
663 if (curStaticInst && curStaticInst->isMemRef()) {
664 // load or store: just send to dcache
665 Fault fault = curStaticInst->initiateAcc(this, traceData);
666
667 // If we're not running now the instruction will complete in a dcache
668 // response callback or the instruction faulted and has started an
669 // ifetch
670 if (_status == Running) {
671 if (fault != NoFault && traceData) {
672 // If there was a fault, we shouldn't trace this instruction.
673 delete traceData;
674 traceData = NULL;
675 }
676
677 postExecute();
678 // @todo remove me after debugging with legion done
679 if (curStaticInst && (!curStaticInst->isMicroop() ||
680 curStaticInst->isFirstMicroop()))
681 instCnt++;
682 advanceInst(fault);
683 }
684 } else if (curStaticInst) {
685 // non-memory instruction: execute completely now
686 Fault fault = curStaticInst->execute(this, traceData);
687
688 // keep an instruction count
689 if (fault == NoFault)
690 countInst();
691 else if (traceData && !DTRACE(ExecFaulting)) {
692 delete traceData;
693 traceData = NULL;
694 }
695
696 postExecute();
697 // @todo remove me after debugging with legion done
698 if (curStaticInst && (!curStaticInst->isMicroop() ||
699 curStaticInst->isFirstMicroop()))
700 instCnt++;
701 advanceInst(fault);
702 } else {
703 advanceInst(NoFault);
704 }
705
706 if (pkt) {
707 delete pkt->req;
708 delete pkt;
709 }
710}
711
712void
713TimingSimpleCPU::IcachePort::ITickEvent::process()
714{
715 cpu->completeIfetch(pkt);
716}
717
718bool
719TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
720{
721 if (pkt->isResponse() && !pkt->wasNacked()) {
722 DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr());
723 // delay processing of returned data until next CPU clock edge
724 Tick next_tick = cpu->nextCycle(curTick());
725
726 if (next_tick == curTick())
727 cpu->completeIfetch(pkt);
728 else
729 tickEvent.schedule(pkt, next_tick);
730
731 return true;
732 } else if (pkt->wasNacked()) {
733 assert(cpu->_status == IcacheWaitResponse);
734 pkt->reinitNacked();
735 if (!sendTiming(pkt)) {
736 cpu->_status = IcacheRetry;
737 cpu->ifetch_pkt = pkt;
738 }
739 }
740 //Snooping a Coherence Request, do nothing
741 return true;
742}
743
744void
745TimingSimpleCPU::IcachePort::recvRetry()
746{
747 // we shouldn't get a retry unless we have a packet that we're
748 // waiting to transmit
749 assert(cpu->ifetch_pkt != NULL);
750 assert(cpu->_status == IcacheRetry);
751 PacketPtr tmp = cpu->ifetch_pkt;
752 if (sendTiming(tmp)) {
753 cpu->_status = IcacheWaitResponse;
754 cpu->ifetch_pkt = NULL;
755 }
756}
757
758void
759TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
760{
761 // received a response from the dcache: complete the load or store
762 // instruction
763 assert(!pkt->isError());
764 assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
765 pkt->req->getFlags().isSet(Request::NO_ACCESS));
766
767 numCycles += tickToCycles(curTick() - previousTick);
768 previousTick = curTick();
769
770 if (pkt->senderState) {
771 SplitFragmentSenderState * send_state =
772 dynamic_cast<SplitFragmentSenderState *>(pkt->senderState);
773 assert(send_state);
774 delete pkt->req;
775 delete pkt;
776 PacketPtr big_pkt = send_state->bigPkt;
777 delete send_state;
778
779 SplitMainSenderState * main_send_state =
780 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
781 assert(main_send_state);
782 // Record the fact that this packet is no longer outstanding.
783 assert(main_send_state->outstanding != 0);
784 main_send_state->outstanding--;
785
786 if (main_send_state->outstanding) {
787 return;
788 } else {
789 delete main_send_state;
790 big_pkt->senderState = NULL;
791 pkt = big_pkt;
792 }
793 }
794
795 _status = Running;
796
797 Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
798
799 // keep an instruction count
800 if (fault == NoFault)
801 countInst();
802 else if (traceData) {
803 // If there was a fault, we shouldn't trace this instruction.
804 delete traceData;
805 traceData = NULL;
806 }
807
808 // the locked flag may be cleared on the response packet, so check
809 // pkt->req and not pkt to see if it was a load-locked
810 if (pkt->isRead() && pkt->req->isLLSC()) {
811 TheISA::handleLockedRead(thread, pkt->req);
812 }
813
814 delete pkt->req;
815 delete pkt;
816
817 postExecute();
818
819 if (getState() == SimObject::Draining) {
820 advancePC(fault);
821 completeDrain();
822
823 return;
824 }
825
826 advanceInst(fault);
827}
828
829
830void
831TimingSimpleCPU::completeDrain()
832{
833 DPRINTF(Config, "Done draining\n");
834 changeState(SimObject::Drained);
835 drainEvent->process();
836}
837
838bool
839TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
840{
841 if (pkt->isResponse() && !pkt->wasNacked()) {
842 // delay processing of returned data until next CPU clock edge
843 Tick next_tick = cpu->nextCycle(curTick());
844
845 if (next_tick == curTick()) {
846 cpu->completeDataAccess(pkt);
847 } else {
848 if (!tickEvent.scheduled()) {
849 tickEvent.schedule(pkt, next_tick);
850 } else {
851 // In the case of a split transaction and a cache that is
852 // faster than a CPU we could get two responses before
853 // next_tick expires
854 if (!retryEvent.scheduled())
855 cpu->schedule(retryEvent, next_tick);
856 return false;
857 }
858 }
859
860 return true;
861 }
862 else if (pkt->wasNacked()) {
863 assert(cpu->_status == DcacheWaitResponse);
864 pkt->reinitNacked();
865 if (!sendTiming(pkt)) {
866 cpu->_status = DcacheRetry;
867 cpu->dcache_pkt = pkt;
868 }
869 }
870 //Snooping a Coherence Request, do nothing
871 return true;
872}
873
874void
875TimingSimpleCPU::DcachePort::DTickEvent::process()
876{
877 cpu->completeDataAccess(pkt);
878}
879
880void
881TimingSimpleCPU::DcachePort::recvRetry()
882{
883 // we shouldn't get a retry unless we have a packet that we're
884 // waiting to transmit
885 assert(cpu->dcache_pkt != NULL);
886 assert(cpu->_status == DcacheRetry);
887 PacketPtr tmp = cpu->dcache_pkt;
888 if (tmp->senderState) {
889 // This is a packet from a split access.
890 SplitFragmentSenderState * send_state =
891 dynamic_cast<SplitFragmentSenderState *>(tmp->senderState);
892 assert(send_state);
893 PacketPtr big_pkt = send_state->bigPkt;
894
895 SplitMainSenderState * main_send_state =
896 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
897 assert(main_send_state);
898
899 if (sendTiming(tmp)) {
900 // If we were able to send without retrying, record that fact
901 // and try sending the other fragment.
902 send_state->clearFromParent();
903 int other_index = main_send_state->getPendingFragment();
904 if (other_index > 0) {
905 tmp = main_send_state->fragments[other_index];
906 cpu->dcache_pkt = tmp;
907 if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) ||
908 (big_pkt->isWrite() && cpu->handleWritePacket())) {
909 main_send_state->fragments[other_index] = NULL;
910 }
911 } else {
912 cpu->_status = DcacheWaitResponse;
913 // memory system takes ownership of packet
914 cpu->dcache_pkt = NULL;
915 }
916 }
917 } else if (sendTiming(tmp)) {
918 cpu->_status = DcacheWaitResponse;
919 // memory system takes ownership of packet
920 cpu->dcache_pkt = NULL;
921 }
922}
923
924TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu,
925 Tick t)
926 : pkt(_pkt), cpu(_cpu)
927{
928 cpu->schedule(this, t);
929}
930
931void
932TimingSimpleCPU::IprEvent::process()
933{
934 cpu->completeDataAccess(pkt);
935}
936
937const char *
938TimingSimpleCPU::IprEvent::description() const
939{
940 return "Timing Simple CPU Delay IPR event";
941}
942
943
944void
945TimingSimpleCPU::printAddr(Addr a)
946{
947 dcachePort.printAddr(a);
948}
949
950
951////////////////////////////////////////////////////////////////////////
952//
953// TimingSimpleCPU Simulation Object
954//
955TimingSimpleCPU *
956TimingSimpleCPUParams::create()
957{
958 numThreads = 1;
959 if (!FullSystem && workload.size() != 1)
960 panic("only one workload allowed");
961 return new TimingSimpleCPU(this);
962}