1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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229{
230 RequestPtr req = pkt->req;
231 if (req->isMmappedIpr()) {
232 Tick delay;
233 delay = TheISA::handleIprRead(thread->getTC(), pkt);
234 new IprEvent(pkt, this, nextCycle(curTick() + delay));
235 _status = DcacheWaitResponse;
236 dcache_pkt = NULL;
237 } else if (!dcachePort.sendTimingReq(pkt)) {
238 _status = DcacheRetry;
239 dcache_pkt = pkt;
240 } else {
241 _status = DcacheWaitResponse;
242 // memory system takes ownership of packet
243 dcache_pkt = NULL;
244 }
245 return dcache_pkt == NULL;

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444{
445 RequestPtr req = dcache_pkt->req;
446 if (req->isMmappedIpr()) {
447 Tick delay;
448 delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
449 new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay));
450 _status = DcacheWaitResponse;
451 dcache_pkt = NULL;
452 } else if (!dcachePort.sendTimingReq(dcache_pkt)) {
453 _status = DcacheRetry;
454 } else {
455 _status = DcacheWaitResponse;
456 // memory system takes ownership of packet
457 dcache_pkt = NULL;
458 }
459 return dcache_pkt == NULL;
460}

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576{
577 if (fault == NoFault) {
578 DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n",
579 req->getVaddr(), req->getPaddr());
580 ifetch_pkt = new Packet(req, MemCmd::ReadReq);
581 ifetch_pkt->dataStatic(&inst);
582 DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr());
583
584 if (!icachePort.sendTimingReq(ifetch_pkt)) {
585 // Need to wait for retry
586 _status = IcacheRetry;
587 } else {
588 // Need to wait for cache to respond
589 _status = IcacheWaitResponse;
590 // ownership of packet transferred to memory system
591 ifetch_pkt = NULL;
592 }

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710
711void
712TimingSimpleCPU::IcachePort::ITickEvent::process()
713{
714 cpu->completeIfetch(pkt);
715}
716
717bool
718TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt)
719{
720 if (!pkt->wasNacked()) {
721 DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr());
722 // delay processing of returned data until next CPU clock edge
723 Tick next_tick = cpu->nextCycle(curTick());
724
725 if (next_tick == curTick())
726 cpu->completeIfetch(pkt);
727 else
728 tickEvent.schedule(pkt, next_tick);
729
730 return true;
731 } else {
732 assert(cpu->_status == IcacheWaitResponse);
733 pkt->reinitNacked();
734 if (!sendTimingReq(pkt)) {
735 cpu->_status = IcacheRetry;
736 cpu->ifetch_pkt = pkt;
737 }
738 }
739
740 return true;
741}
742
743void
744TimingSimpleCPU::IcachePort::recvRetry()
745{
746 // we shouldn't get a retry unless we have a packet that we're
747 // waiting to transmit
748 assert(cpu->ifetch_pkt != NULL);
749 assert(cpu->_status == IcacheRetry);
750 PacketPtr tmp = cpu->ifetch_pkt;
751 if (sendTimingReq(tmp)) {
752 cpu->_status = IcacheWaitResponse;
753 cpu->ifetch_pkt = NULL;
754 }
755}
756
757void
758TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
759{

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830TimingSimpleCPU::completeDrain()
831{
832 DPRINTF(Config, "Done draining\n");
833 changeState(SimObject::Drained);
834 drainEvent->process();
835}
836
837bool
838TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt)
839{
840 if (!pkt->wasNacked()) {
841 // delay processing of returned data until next CPU clock edge
842 Tick next_tick = cpu->nextCycle(curTick());
843
844 if (next_tick == curTick()) {
845 cpu->completeDataAccess(pkt);
846 } else {
847 if (!tickEvent.scheduled()) {

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855 return false;
856 }
857 }
858
859 return true;
860 } else {
861 assert(cpu->_status == DcacheWaitResponse);
862 pkt->reinitNacked();
863 if (!sendTimingReq(pkt)) {
864 cpu->_status = DcacheRetry;
865 cpu->dcache_pkt = pkt;
866 }
867 }
868
869 return true;
870}
871

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889 dynamic_cast<SplitFragmentSenderState *>(tmp->senderState);
890 assert(send_state);
891 PacketPtr big_pkt = send_state->bigPkt;
892
893 SplitMainSenderState * main_send_state =
894 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
895 assert(main_send_state);
896
897 if (sendTimingReq(tmp)) {
898 // If we were able to send without retrying, record that fact
899 // and try sending the other fragment.
900 send_state->clearFromParent();
901 int other_index = main_send_state->getPendingFragment();
902 if (other_index > 0) {
903 tmp = main_send_state->fragments[other_index];
904 cpu->dcache_pkt = tmp;
905 if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) ||
906 (big_pkt->isWrite() && cpu->handleWritePacket())) {
907 main_send_state->fragments[other_index] = NULL;
908 }
909 } else {
910 cpu->_status = DcacheWaitResponse;
911 // memory system takes ownership of packet
912 cpu->dcache_pkt = NULL;
913 }
914 }
915 } else if (sendTimingReq(tmp)) {
916 cpu->_status = DcacheWaitResponse;
917 // memory system takes ownership of packet
918 cpu->dcache_pkt = NULL;
919 }
920}
921
922TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu,
923 Tick t)

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