1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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474 DataTranslation<TimingSimpleCPU> *translation
475 = new DataTranslation<TimingSimpleCPU>(this, state);
476 thread->dtb->translateTiming(req, tc, translation, mode);
477 }
478
479 return NoFault;
480}
481
482bool
483TimingSimpleCPU::handleWritePacket()
484{
485 RequestPtr req = dcache_pkt->req;
486 if (req->isMmappedIpr()) {
487 Tick delay;
488 delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
489 new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay));

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495 _status = DcacheWaitResponse;
496 // memory system takes ownership of packet
497 dcache_pkt = NULL;
498 }
499 return dcache_pkt == NULL;
500}
501
502Fault
503TimingSimpleCPU::writeBytes(uint8_t *data, unsigned size,
504 Addr addr, unsigned flags, uint64_t *res)
505{
506 uint8_t *newData = new uint8_t[size];
507 memcpy(newData, data, size);
508
509 const int asid = 0;
510 const ThreadID tid = 0;
511 const Addr pc = thread->instAddr();
512 unsigned block_size = dcachePort.peerBlockSize();
513 BaseTLB::Mode mode = BaseTLB::Write;
514
515 if (traceData) {
516 traceData->setAddr(addr);

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524
525 _status = DTBWaitResponse;
526 if (split_addr > addr) {
527 RequestPtr req1, req2;
528 assert(!req->isLLSC() && !req->isSwap());
529 req->splitOnVaddr(split_addr, req1, req2);
530
531 WholeTranslationState *state =
532 new WholeTranslationState(req, req1, req2, newData, res, mode);
533 DataTranslation<TimingSimpleCPU> *trans1 =
534 new DataTranslation<TimingSimpleCPU>(this, state, 0);
535 DataTranslation<TimingSimpleCPU> *trans2 =
536 new DataTranslation<TimingSimpleCPU>(this, state, 1);
537
538 thread->dtb->translateTiming(req1, tc, trans1, mode);
539 thread->dtb->translateTiming(req2, tc, trans2, mode);
540 } else {
541 WholeTranslationState *state =
542 new WholeTranslationState(req, newData, res, mode);
543 DataTranslation<TimingSimpleCPU> *translation =
544 new DataTranslation<TimingSimpleCPU>(this, state);
545 thread->dtb->translateTiming(req, tc, translation, mode);
546 }
547
548 // Translation faults will be returned via finishTranslation()
549 return NoFault;
550}
551
552
553void
554TimingSimpleCPU::finishTranslation(WholeTranslationState *state)
555{
556 _status = Running;
557
558 if (state->getFault() != NoFault) {
559 if (state->isPrefetch()) {
560 state->setNoFault();

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