1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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52 else
53 panic("No Such Port\n");
54}
55
56void
57TimingSimpleCPU::init()
58{
59 BaseCPU::init();
60#if FULL_SYSTEM
61 for (int i = 0; i < threadContexts.size(); ++i) {
62 ThreadContext *tc = threadContexts[i];
63
64 // initialize CPU, including PC
65 TheISA::initCPU(tc, _cpuId);
66 }
67#endif
68}
69
70Tick
71TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
72{
73 panic("TimingSimpleCPU doesn't expect recvAtomic callback!");

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197 break;
198 }
199 }
200
201 if (_status != Running) {
202 _status = Idle;
203 }
204 assert(threadContexts.size() == 1);
205 _cpuId = tc->cpuId();
206 previousTick = curTick;
207}
208
209
210void
211TimingSimpleCPU::activateContext(int thread_num, int delay)
212{
213 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);

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244
245
246template <class T>
247Fault
248TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
249{
250 Request *req =
251 new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
252 _cpuId, /* thread ID */ 0);
253
254 if (traceData) {
255 traceData->setAddr(req->getVaddr());
256 }
257
258 // translate to physical address
259 Fault fault = thread->translateDataReadReq(req);
260

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295 return fault;
296}
297
298Fault
299TimingSimpleCPU::translateDataReadAddr(Addr vaddr, Addr &paddr,
300 int size, unsigned flags)
301{
302 Request *req =
303 new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0);
304
305 if (traceData) {
306 traceData->setAddr(vaddr);
307 }
308
309 Fault fault = thread->translateDataWriteReq(req);
310
311 if (fault == NoFault)

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367
368
369template <class T>
370Fault
371TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
372{
373 Request *req =
374 new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
375 _cpuId, /* thread ID */ 0);
376
377 if (traceData) {
378 traceData->setAddr(req->getVaddr());
379 }
380
381 // translate to physical address
382 Fault fault = thread->translateDataWriteReq(req);
383

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436 return fault;
437}
438
439Fault
440TimingSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr,
441 int size, unsigned flags)
442{
443 Request *req =
444 new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0);
445
446 if (traceData) {
447 traceData->setAddr(vaddr);
448 }
449
450 Fault fault = thread->translateDataWriteReq(req);
451
452 if (fault == NoFault)

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522 checkForInterrupts();
523
524 checkPcEventQueue();
525
526 bool fromRom = isRomMicroPC(thread->readMicroPC());
527
528 if (!fromRom) {
529 Request *ifetch_req = new Request();
530 ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
531 Fault fault = setupFetchRequest(ifetch_req);
532
533 ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
534 ifetch_pkt->dataStatic(&inst);
535
536 if (fault == NoFault) {
537 if (!icachePort.sendTiming(ifetch_pkt)) {
538 // Need to wait for retry

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