1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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569
570 if (next_tick == curTick)
571 cpu->completeIfetch(pkt);
572 else
573 tickEvent.schedule(pkt, next_tick);
574
575 return true;
576 }
577 else if (pkt->result == Packet::Nacked) {
578 assert(cpu->_status == IcacheWaitResponse);
579 pkt->reinitNacked();
580 if (!sendTiming(pkt)) {
581 cpu->_status = IcacheRetry;
582 cpu->ifetch_pkt = pkt;
583 }
584 }
585 //Snooping a Coherence Request, do nothing
586 return true;
587}
588
589void
590TimingSimpleCPU::IcachePort::recvRetry()
591{
592 // we shouldn't get a retry unless we have a packet that we're
593 // waiting to transmit
594 assert(cpu->ifetch_pkt != NULL);

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664
665 if (next_tick == curTick)
666 cpu->completeDataAccess(pkt);
667 else
668 tickEvent.schedule(pkt, next_tick);
669
670 return true;
671 }
672 else if (pkt->result == Packet::Nacked) {
673 assert(cpu->_status == DcacheWaitResponse);
674 pkt->reinitNacked();
675 if (!sendTiming(pkt)) {
676 cpu->_status = DcacheRetry;
677 cpu->dcache_pkt = pkt;
678 }
679 }
680 //Snooping a Coherence Request, do nothing
681 return true;
682}
683
684void
685TimingSimpleCPU::DcachePort::DTickEvent::process()
686{
687 cpu->completeDataAccess(pkt);
688}
689

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