1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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77{
78 //No internal storage to update, jusst return
79 return;
80}
81
82void
83TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
84{
85 if (status == RangeChange) {
86 if (!snoopRangeSent) {
87 snoopRangeSent = true;
88 sendStatusChange(Port::RangeChange);
89 }
90 return;
91 }
92
93 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
94}
95
96
97void
98TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
99{
100 pkt = _pkt;
101 Event::schedule(t);
102}
103
104TimingSimpleCPU::TimingSimpleCPU(Params *p)
105 : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock),
106 cpu_id(p->cpu_id)
107{
108 _status = Idle;
109
110 icachePort.snoopRangeSent = false;
111 dcachePort.snoopRangeSent = false;
112
113 ifetch_pkt = dcache_pkt = NULL;
114 drainEvent = NULL;
115 fetchEvent = NULL;
116 previousTick = 0;
117 changeState(SimObject::Running);
118}
119
120

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164 if (fetchEvent->scheduled())
165 fetchEvent->deschedule();
166
167 delete fetchEvent;
168 }
169
170 fetchEvent =
171 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
172 fetchEvent->schedule(nextCycle());
173 }
174
175 changeState(SimObject::Running);
176 previousTick = curTick;
177}
178
179void
180TimingSimpleCPU::switchOut()

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236
237 assert(_status == Idle);
238
239 notIdleFraction++;
240 _status = Running;
241 // kick things off by initiating the fetch of the next instruction
242 fetchEvent =
243 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
244 fetchEvent->schedule(nextCycle(curTick + cycles(delay)));
245}
246
247
248void
249TimingSimpleCPU::suspendContext(int thread_num)
250{
251 assert(thread_num == 0);
252 assert(thread);

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285 if (!dcachePort.sendTiming(pkt)) {
286 _status = DcacheRetry;
287 dcache_pkt = pkt;
288 } else {
289 _status = DcacheWaitResponse;
290 // memory system takes ownership of packet
291 dcache_pkt = NULL;
292 }
293 }
294
295 // This will need a new way to tell if it has a dcache attached.
296 if (req->isUncacheable())
297 recordEvent("Uncached Read");
298
299 return fault;
300}

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370 if (!dcachePort.sendTiming(dcache_pkt)) {
371 _status = DcacheRetry;
372 } else {
373 _status = DcacheWaitResponse;
374 // memory system takes ownership of packet
375 dcache_pkt = NULL;
376 }
377 }
378 }
379
380 // This will need a new way to tell if it's hooked up to a cache or not.
381 if (req->isUncacheable())
382 recordEvent("Uncached Write");
383
384 // If the write needs to have a fault on the access, consider calling
385 // changeStatus() and changing it to "bad addr write" or something.

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452 _status = IcacheRetry;
453 } else {
454 // Need to wait for cache to respond
455 _status = IcacheWaitResponse;
456 // ownership of packet transferred to memory system
457 ifetch_pkt = NULL;
458 }
459 } else {
460 // fetch fault: advance directly to next instruction (fault handler)
461 advanceInst(fault);
462 }
463
464 numCycles += curTick - previousTick;
465 previousTick = curTick;
466}
467

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485{
486 // received a response from the icache: execute the received
487 // instruction
488 assert(pkt->result == Packet::Success);
489 assert(_status == IcacheWaitResponse);
490
491 _status = Running;
492
493 delete pkt->req;
494 delete pkt;
495
496 numCycles += curTick - previousTick;
497 previousTick = curTick;
498
499 if (getState() == SimObject::Draining) {
500 completeDrain();
501 return;
502 }
503
504 preExecute();
505 if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
506 // load or store: just send to dcache
507 Fault fault = curStaticInst->initiateAcc(this, traceData);

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523 advanceInst(fault);
524 }
525 } else {
526 // non-memory instruction: execute completely now
527 Fault fault = curStaticInst->execute(this, traceData);
528 postExecute();
529 advanceInst(fault);
530 }
531}
532
533void
534TimingSimpleCPU::IcachePort::ITickEvent::process()
535{
536 cpu->completeIfetch(pkt);
537}
538

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678 Param<bool> do_quiesce;
679 Param<bool> do_checkpoint_insts;
680 Param<bool> do_statistics_insts;
681#else
682 SimObjectParam<Process *> workload;
683#endif // FULL_SYSTEM
684
685 Param<int> clock;
686 Param<int> phase;
687
688 Param<bool> defer_registration;
689 Param<int> width;
690 Param<bool> function_trace;
691 Param<Tick> function_trace_start;
692 Param<bool> simulate_stalls;
693
694END_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)

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714 INIT_PARAM(do_quiesce, ""),
715 INIT_PARAM(do_checkpoint_insts, ""),
716 INIT_PARAM(do_statistics_insts, ""),
717#else
718 INIT_PARAM(workload, "processes to run"),
719#endif // FULL_SYSTEM
720
721 INIT_PARAM(clock, "clock speed"),
722 INIT_PARAM_DFLT(phase, "clock phase", 0),
723 INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
724 INIT_PARAM(width, "cpu width"),
725 INIT_PARAM(function_trace, "Enable function trace"),
726 INIT_PARAM(function_trace_start, "Cycle to start function trace"),
727 INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
728
729END_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
730

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736 params->numberOfThreads = 1;
737 params->max_insts_any_thread = max_insts_any_thread;
738 params->max_insts_all_threads = max_insts_all_threads;
739 params->max_loads_any_thread = max_loads_any_thread;
740 params->max_loads_all_threads = max_loads_all_threads;
741 params->progress_interval = progress_interval;
742 params->deferRegistration = defer_registration;
743 params->clock = clock;
744 params->phase = phase;
745 params->functionTrace = function_trace;
746 params->functionTraceStart = function_trace_start;
747 params->system = system;
748 params->cpu_id = cpu_id;
749
750#if FULL_SYSTEM
751 params->itb = itb;
752 params->dtb = dtb;

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