1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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77{
78 //No internal storage to update, jusst return
79 return;
80}
81
82void
83TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
84{
85 if (status == RangeChange)
86 return;
87
88 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
89}
90
91
92void
93TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
94{
95 pkt = _pkt;
96 Event::schedule(t);
97}
98
99TimingSimpleCPU::TimingSimpleCPU(Params *p)
100 : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock),
101 cpu_id(p->cpu_id)
102{
103 _status = Idle;
104 ifetch_pkt = dcache_pkt = NULL;
105 drainEvent = NULL;
106 fetchEvent = NULL;
107 previousTick = 0;
108 changeState(SimObject::Running);
109}
110
111

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276 if (!dcachePort.sendTiming(pkt)) {
277 _status = DcacheRetry;
278 dcache_pkt = pkt;
279 } else {
280 _status = DcacheWaitResponse;
281 // memory system takes ownership of packet
282 dcache_pkt = NULL;
283 }
284 } else {
285 delete req;
286 }
287
288 // This will need a new way to tell if it has a dcache attached.
289 if (req->isUncacheable())
290 recordEvent("Uncached Read");
291
292 return fault;
293}

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363 if (!dcachePort.sendTiming(dcache_pkt)) {
364 _status = DcacheRetry;
365 } else {
366 _status = DcacheWaitResponse;
367 // memory system takes ownership of packet
368 dcache_pkt = NULL;
369 }
370 }
371 } else {
372 delete req;
373 }
374
375 // This will need a new way to tell if it's hooked up to a cache or not.
376 if (req->isUncacheable())
377 recordEvent("Uncached Write");
378
379 // If the write needs to have a fault on the access, consider calling
380 // changeStatus() and changing it to "bad addr write" or something.

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447 _status = IcacheRetry;
448 } else {
449 // Need to wait for cache to respond
450 _status = IcacheWaitResponse;
451 // ownership of packet transferred to memory system
452 ifetch_pkt = NULL;
453 }
454 } else {
455 delete ifetch_req;
456 delete ifetch_pkt;
457 // fetch fault: advance directly to next instruction (fault handler)
458 advanceInst(fault);
459 }
460
461 numCycles += curTick - previousTick;
462 previousTick = curTick;
463}
464

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482{
483 // received a response from the icache: execute the received
484 // instruction
485 assert(pkt->result == Packet::Success);
486 assert(_status == IcacheWaitResponse);
487
488 _status = Running;
489
490 numCycles += curTick - previousTick;
491 previousTick = curTick;
492
493 if (getState() == SimObject::Draining) {
494 delete pkt->req;
495 delete pkt;
496
497 completeDrain();
498 return;
499 }
500
501 preExecute();
502 if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
503 // load or store: just send to dcache
504 Fault fault = curStaticInst->initiateAcc(this, traceData);

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520 advanceInst(fault);
521 }
522 } else {
523 // non-memory instruction: execute completely now
524 Fault fault = curStaticInst->execute(this, traceData);
525 postExecute();
526 advanceInst(fault);
527 }
528
529 delete pkt->req;
530 delete pkt;
531}
532
533void
534TimingSimpleCPU::IcachePort::ITickEvent::process()
535{
536 cpu->completeIfetch(pkt);
537}
538

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