1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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83 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
84}
85
86TimingSimpleCPU::TimingSimpleCPU(Params *p)
87 : BaseSimpleCPU(p), icachePort(this), dcachePort(this)
88{
89 _status = Idle;
90 ifetch_pkt = dcache_pkt = NULL;
91 quiesceEvent = NULL;
92 state = SimObject::Timing;
93}
94
95
96TimingSimpleCPU::~TimingSimpleCPU()
97{
98}
99
100void
101TimingSimpleCPU::serialize(ostream &os)
102{
103 SERIALIZE_ENUM(_status);
104 BaseSimpleCPU::serialize(os);
105}
106
107void
108TimingSimpleCPU::unserialize(Checkpoint *cp, const string &section)
109{
110 UNSERIALIZE_ENUM(_status);
111 BaseSimpleCPU::unserialize(cp, section);
112}
113
114bool
115TimingSimpleCPU::quiesce(Event *quiesce_event)
116{
117 // TimingSimpleCPU is ready to quiesce if it's not waiting for
118 // an access to complete.
119 if (status() == Idle || status() == Running || status() == SwitchedOut) {
120 DPRINTF(Config, "Ready to quiesce\n");
121 return false;
122 } else {
123 DPRINTF(Config, "Waiting to quiesce\n");
124 changeState(SimObject::Quiescing);
125 quiesceEvent = quiesce_event;
126 return true;
127 }
128}
129
130void
131TimingSimpleCPU::resume()
132{
133 if (_status != SwitchedOut && _status != Idle) {
134 Event *e =
135 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, true);
136 e->schedule(curTick);
137 }
138}
139
140void
141TimingSimpleCPU::setMemoryMode(State new_mode)
142{
143 assert(new_mode == SimObject::Timing);
144}
145
146void
147TimingSimpleCPU::switchOut()
148{
149 assert(status() == Running || status() == Idle);
150 _status = SwitchedOut;
151}
152
153
154void
155TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
156{
157 BaseCPU::takeOverFrom(oldCPU);
158
159 // if any of this CPU's ThreadContexts are active, mark the CPU as
160 // running and schedule its tick event.
161 for (int i = 0; i < threadContexts.size(); ++i) {
162 ThreadContext *tc = threadContexts[i];

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409
410void
411TimingSimpleCPU::completeIfetch(Packet *pkt)
412{
413 // received a response from the icache: execute the received
414 // instruction
415 assert(pkt->result == Packet::Success);
416 assert(_status == IcacheWaitResponse);
417
418 _status = Running;
419
420 delete pkt->req;
421 delete pkt;
422
423 if (getState() == SimObject::Quiescing) {
424 completeQuiesce();
425 return;
426 }
427
428 preExecute();
429 if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
430 // load or store: just send to dcache
431 Fault fault = curStaticInst->initiateAcc(this, traceData);
432 if (fault == NoFault) {
433 // successfully initiated access: instruction will
434 // complete in dcache response callback
435 assert(_status == DcacheWaitResponse);

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472TimingSimpleCPU::completeDataAccess(Packet *pkt)
473{
474 // received a response from the dcache: complete the load or store
475 // instruction
476 assert(pkt->result == Packet::Success);
477 assert(_status == DcacheWaitResponse);
478 _status = Running;
479
480 if (getState() == SimObject::Quiescing) {
481 completeQuiesce();
482
483 delete pkt->req;
484 delete pkt;
485
486 return;
487 }
488
489 Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
490
491 delete pkt->req;
492 delete pkt;
493
494 postExecute();
495 advanceInst(fault);
496}
497
498
499void
500TimingSimpleCPU::completeQuiesce()
501{
502 DPRINTF(Config, "Done quiescing\n");
503 changeState(SimObject::QuiescedTiming);
504 quiesceEvent->process();
505}
506
507bool
508TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
509{
510 cpu->completeDataAccess(pkt);
511 return true;
512}
513

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