1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Dam Sunwoo
38 * Curtis Dunham
39 */
40
41#ifndef __CPU_SIMPLE_PROBES_SIMPOINT_HH__
42#define __CPU_SIMPLE_PROBES_SIMPOINT_HH__
43
44#include <unordered_map>
45
| 1/*
2 * Copyright (c) 2012-2014 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Dam Sunwoo
38 * Curtis Dunham
39 */
40
41#ifndef __CPU_SIMPLE_PROBES_SIMPOINT_HH__
42#define __CPU_SIMPLE_PROBES_SIMPOINT_HH__
43
44#include <unordered_map>
45
|
46#include "cpu/simple_thread.hh"
47#include "params/SimPoint.hh"
48#include "sim/probe/probe.hh"
49
50/**
51 * Probe for SimPoints BBV generation
52 */
53
54/**
55 * Start and end address of basic block for SimPoint profiling.
56 * This structure is used to look up the hash table of BBVs.
57 * - first: PC of first inst in basic block
58 * - second: PC of last inst in basic block
59 */
60typedef std::pair<Addr, Addr> BasicBlockRange;
61
62/** Overload hash function for BasicBlockRange type */
63namespace std {
64template <>
65struct hash<BasicBlockRange>
66{
67 public:
68 size_t operator()(const BasicBlockRange &bb) const {
69 return hash<Addr>()(bb.first + bb.second);
70 }
71};
72}
73
74class SimPoint : public ProbeListenerObject
75{
76 public:
77 SimPoint(const SimPointParams *params);
78 virtual ~SimPoint();
79
80 virtual void init();
81
82 virtual void regProbeListeners();
83
84 /**
85 * Profile basic blocks for SimPoints.
86 * Called at every macro inst to increment basic block inst counts and
87 * to profile block if end of block.
88 */
89 void profile(const std::pair<SimpleThread*, StaticInstPtr>&);
90
91 private:
92 /** SimPoint profiling interval size in instructions */
93 const uint64_t intervalSize;
94
95 /** Inst count in current basic block */
96 uint64_t intervalCount;
97 /** Excess inst count from previous interval*/
98 uint64_t intervalDrift;
99 /** Pointer to SimPoint BBV output stream */
| 47#include "cpu/simple_thread.hh"
48#include "params/SimPoint.hh"
49#include "sim/probe/probe.hh"
50
51/**
52 * Probe for SimPoints BBV generation
53 */
54
55/**
56 * Start and end address of basic block for SimPoint profiling.
57 * This structure is used to look up the hash table of BBVs.
58 * - first: PC of first inst in basic block
59 * - second: PC of last inst in basic block
60 */
61typedef std::pair<Addr, Addr> BasicBlockRange;
62
63/** Overload hash function for BasicBlockRange type */
64namespace std {
65template <>
66struct hash<BasicBlockRange>
67{
68 public:
69 size_t operator()(const BasicBlockRange &bb) const {
70 return hash<Addr>()(bb.first + bb.second);
71 }
72};
73}
74
75class SimPoint : public ProbeListenerObject
76{
77 public:
78 SimPoint(const SimPointParams *params);
79 virtual ~SimPoint();
80
81 virtual void init();
82
83 virtual void regProbeListeners();
84
85 /**
86 * Profile basic blocks for SimPoints.
87 * Called at every macro inst to increment basic block inst counts and
88 * to profile block if end of block.
89 */
90 void profile(const std::pair<SimpleThread*, StaticInstPtr>&);
91
92 private:
93 /** SimPoint profiling interval size in instructions */
94 const uint64_t intervalSize;
95
96 /** Inst count in current basic block */
97 uint64_t intervalCount;
98 /** Excess inst count from previous interval*/
99 uint64_t intervalDrift;
100 /** Pointer to SimPoint BBV output stream */
|
101
102 /** Basic Block information */
103 struct BBInfo {
104 /** Unique ID */
105 uint64_t id;
106 /** Num of static insts in BB */
107 uint64_t insts;
108 /** Accumulated dynamic inst count executed by BB */
109 uint64_t count;
110 };
111
112 /** Hash table containing all previously seen basic blocks */
113 std::unordered_map<BasicBlockRange, BBInfo> bbMap;
114 /** Currently executing basic block */
115 BasicBlockRange currentBBV;
116 /** inst count in current basic block */
117 uint64_t currentBBVInstCount;
118};
119
120#endif // __CPU_SIMPLE_PROBES_SIMPOINT_HH__
| 102
103 /** Basic Block information */
104 struct BBInfo {
105 /** Unique ID */
106 uint64_t id;
107 /** Num of static insts in BB */
108 uint64_t insts;
109 /** Accumulated dynamic inst count executed by BB */
110 uint64_t count;
111 };
112
113 /** Hash table containing all previously seen basic blocks */
114 std::unordered_map<BasicBlockRange, BBInfo> bbMap;
115 /** Currently executing basic block */
116 BasicBlockRange currentBBV;
117 /** inst count in current basic block */
118 uint64_t currentBBVInstCount;
119};
120
121#endif // __CPU_SIMPLE_PROBES_SIMPOINT_HH__
|