exec_context.hh (13611:c8b7847b4171) exec_context.hh (13622:ba31c2a23eca)
1/*
2 * Copyright (c) 2014-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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55#include "cpu/static_inst_fwd.hh"
56#include "cpu/translation.hh"
57#include "mem/request.hh"
58
59class BaseSimpleCPU;
60
61class SimpleExecContext : public ExecContext {
62 protected:
1/*
2 * Copyright (c) 2014-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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55#include "cpu/static_inst_fwd.hh"
56#include "cpu/translation.hh"
57#include "mem/request.hh"
58
59class BaseSimpleCPU;
60
61class SimpleExecContext : public ExecContext {
62 protected:
63 typedef TheISA::CCReg CCReg;
64 using VecRegContainer = TheISA::VecRegContainer;
65 using VecElem = TheISA::VecElem;
66
67 public:
68 BaseSimpleCPU *cpu;
69 SimpleThread* thread;
70
71 // This is the offset from the current pc that fetch should be performed

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360 const VecPredRegContainer& val) override
361 {
362 numVecPredRegWrites++;
363 const RegId& reg = si->destRegIdx(idx);
364 assert(reg.isVecPredReg());
365 thread->setVecPredReg(reg, val);
366 }
367
63 using VecRegContainer = TheISA::VecRegContainer;
64 using VecElem = TheISA::VecElem;
65
66 public:
67 BaseSimpleCPU *cpu;
68 SimpleThread* thread;
69
70 // This is the offset from the current pc that fetch should be performed

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359 const VecPredRegContainer& val) override
360 {
361 numVecPredRegWrites++;
362 const RegId& reg = si->destRegIdx(idx);
363 assert(reg.isVecPredReg());
364 thread->setVecPredReg(reg, val);
365 }
366
368 CCReg
367 RegVal
369 readCCRegOperand(const StaticInst *si, int idx) override
370 {
371 numCCRegReads++;
372 const RegId& reg = si->srcRegIdx(idx);
373 assert(reg.isCCReg());
374 return thread->readCCReg(reg.index());
375 }
376
377 void
368 readCCRegOperand(const StaticInst *si, int idx) override
369 {
370 numCCRegReads++;
371 const RegId& reg = si->srcRegIdx(idx);
372 assert(reg.isCCReg());
373 return thread->readCCReg(reg.index());
374 }
375
376 void
378 setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
377 setCCRegOperand(const StaticInst *si, int idx, RegVal val) override
379 {
380 numCCRegWrites++;
381 const RegId& reg = si->destRegIdx(idx);
382 assert(reg.isCCReg());
383 thread->setCCReg(reg.index(), val);
384 }
385
386 RegVal

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379 numCCRegWrites++;
380 const RegId& reg = si->destRegIdx(idx);
381 assert(reg.isCCReg());
382 thread->setCCReg(reg.index(), val);
383 }
384
385 RegVal

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