exec_context.hh (13598:39220222740c) exec_context.hh (13610:5d5404ac6288)
1/*
1/*
2 * Copyright (c) 2014-2016 ARM Limited
2 * Copyright (c) 2014-2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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116 // Number of float register file accesses
117 Stats::Scalar numFpRegReads;
118 Stats::Scalar numFpRegWrites;
119
120 // Number of vector register file accesses
121 mutable Stats::Scalar numVecRegReads;
122 Stats::Scalar numVecRegWrites;
123
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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116 // Number of float register file accesses
117 Stats::Scalar numFpRegReads;
118 Stats::Scalar numFpRegWrites;
119
120 // Number of vector register file accesses
121 mutable Stats::Scalar numVecRegReads;
122 Stats::Scalar numVecRegWrites;
123
124 // Number of predicate register file accesses
125 mutable Stats::Scalar numVecPredRegReads;
126 Stats::Scalar numVecPredRegWrites;
127
124 // Number of condition code register file accesses
125 Stats::Scalar numCCRegReads;
126 Stats::Scalar numCCRegWrites;
127
128 // Number of simulated memory references
129 Stats::Scalar numMemRefs;
130 Stats::Scalar numLoadInsts;
131 Stats::Scalar numStoreInsts;

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328 const VecElem val) override
329 {
330 numVecRegWrites++;
331 const RegId& reg = si->destRegIdx(idx);
332 assert(reg.isVecElem());
333 thread->setVecElem(reg, val);
334 }
335
128 // Number of condition code register file accesses
129 Stats::Scalar numCCRegReads;
130 Stats::Scalar numCCRegWrites;
131
132 // Number of simulated memory references
133 Stats::Scalar numMemRefs;
134 Stats::Scalar numLoadInsts;
135 Stats::Scalar numStoreInsts;

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332 const VecElem val) override
333 {
334 numVecRegWrites++;
335 const RegId& reg = si->destRegIdx(idx);
336 assert(reg.isVecElem());
337 thread->setVecElem(reg, val);
338 }
339
340 const VecPredRegContainer&
341 readVecPredRegOperand(const StaticInst *si, int idx) const override
342 {
343 numVecPredRegReads++;
344 const RegId& reg = si->srcRegIdx(idx);
345 assert(reg.isVecPredReg());
346 return thread->readVecPredReg(reg);
347 }
348
349 VecPredRegContainer&
350 getWritableVecPredRegOperand(const StaticInst *si, int idx) override
351 {
352 numVecPredRegWrites++;
353 const RegId& reg = si->destRegIdx(idx);
354 assert(reg.isVecPredReg());
355 return thread->getWritableVecPredReg(reg);
356 }
357
358 void
359 setVecPredRegOperand(const StaticInst *si, int idx,
360 const VecPredRegContainer& val) override
361 {
362 numVecPredRegWrites++;
363 const RegId& reg = si->destRegIdx(idx);
364 assert(reg.isVecPredReg());
365 thread->setVecPredReg(reg, val);
366 }
367
336 CCReg
337 readCCRegOperand(const StaticInst *si, int idx) override
338 {
339 numCCRegReads++;
340 const RegId& reg = si->srcRegIdx(idx);
341 assert(reg.isCCReg());
342 return thread->readCCReg(reg.index());
343 }

--- 203 unchanged lines hidden --- 		368 CCReg
369 readCCRegOperand(const StaticInst *si, int idx) override
370 {
371 numCCRegReads++;
372 const RegId& reg = si->srcRegIdx(idx);
373 assert(reg.isCCReg());
374 return thread->readCCReg(reg.index());
375 }

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