exec_context.hh (13582:989577bf6abc) exec_context.hh (13598:39220222740c)
1/*
2 * Copyright (c) 2014-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 303 unchanged lines hidden (view full) ---

312 { return setVecLaneOperandT(si, idx, val); }
313 /** @} */
314
315 /** Reads an element of a vector register. */
316 VecElem
317 readVecElemOperand(const StaticInst *si, int idx) const override
318 {
319 numVecRegReads++;
1/*
2 * Copyright (c) 2014-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 303 unchanged lines hidden (view full) ---

312 { return setVecLaneOperandT(si, idx, val); }
313 /** @} */
314
315 /** Reads an element of a vector register. */
316 VecElem
317 readVecElemOperand(const StaticInst *si, int idx) const override
318 {
319 numVecRegReads++;
320 const RegId& reg = si->destRegIdx(idx);
320 const RegId& reg = si->srcRegIdx(idx);
321 assert(reg.isVecElem());
322 return thread->readVecElem(reg);
323 }
324
325 /** Sets an element of a vector register to a value. */
326 void
327 setVecElemOperand(const StaticInst *si, int idx,
328 const VecElem val) override

--- 218 unchanged lines hidden --- 		321 assert(reg.isVecElem());
322 return thread->readVecElem(reg);
323 }
324
325 /** Sets an element of a vector register to a value. */
326 void
327 setVecElemOperand(const StaticInst *si, int idx,
328 const VecElem val) override

--- 218 unchanged lines hidden ---