exec_context.hh (11877:5ea85692a53e) | exec_context.hh (12104:edd63f9c6184) |
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1/* 2 * Copyright (c) 2014-2015 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 36 unchanged lines hidden (view full) --- 45#ifndef __CPU_SIMPLE_EXEC_CONTEXT_HH__ 46#define __CPU_SIMPLE_EXEC_CONTEXT_HH__ 47 48#include "arch/registers.hh" 49#include "base/types.hh" 50#include "config/the_isa.hh" 51#include "cpu/base.hh" 52#include "cpu/exec_context.hh" | 1/* 2 * Copyright (c) 2014-2015 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 36 unchanged lines hidden (view full) --- 45#ifndef __CPU_SIMPLE_EXEC_CONTEXT_HH__ 46#define __CPU_SIMPLE_EXEC_CONTEXT_HH__ 47 48#include "arch/registers.hh" 49#include "base/types.hh" 50#include "config/the_isa.hh" 51#include "cpu/base.hh" 52#include "cpu/exec_context.hh" |
53#include "cpu/reg_class.hh" |
|
53#include "cpu/simple/base.hh" 54#include "cpu/static_inst_fwd.hh" 55#include "cpu/translation.hh" 56#include "mem/request.hh" 57 58class BaseSimpleCPU; 59 60class SimpleExecContext : public ExecContext { --- 98 unchanged lines hidden (view full) --- 159 : cpu(_cpu), thread(_thread), fetchOffset(0), stayAtPC(false), 160 numInst(0), numOp(0), numLoad(0), lastIcacheStall(0), lastDcacheStall(0) 161 { } 162 163 /** Reads an integer register. */ 164 IntReg readIntRegOperand(const StaticInst *si, int idx) override 165 { 166 numIntRegReads++; | 54#include "cpu/simple/base.hh" 55#include "cpu/static_inst_fwd.hh" 56#include "cpu/translation.hh" 57#include "mem/request.hh" 58 59class BaseSimpleCPU; 60 61class SimpleExecContext : public ExecContext { --- 98 unchanged lines hidden (view full) --- 160 : cpu(_cpu), thread(_thread), fetchOffset(0), stayAtPC(false), 161 numInst(0), numOp(0), numLoad(0), lastIcacheStall(0), lastDcacheStall(0) 162 { } 163 164 /** Reads an integer register. */ 165 IntReg readIntRegOperand(const StaticInst *si, int idx) override 166 { 167 numIntRegReads++; |
167 return thread->readIntReg(si->srcRegIdx(idx)); | 168 RegId reg = si->srcRegIdx(idx); 169 assert(reg.regClass == IntRegClass); 170 return thread->readIntReg(reg.regIdx); |
168 } 169 170 /** Sets an integer register to a value. */ 171 void setIntRegOperand(const StaticInst *si, int idx, IntReg val) override 172 { 173 numIntRegWrites++; | 171 } 172 173 /** Sets an integer register to a value. */ 174 void setIntRegOperand(const StaticInst *si, int idx, IntReg val) override 175 { 176 numIntRegWrites++; |
174 thread->setIntReg(si->destRegIdx(idx), val); | 177 RegId reg = si->destRegIdx(idx); 178 assert(reg.regClass == IntRegClass); 179 thread->setIntReg(reg.regIdx, val); |
175 } 176 177 /** Reads a floating point register of single register width. */ 178 FloatReg readFloatRegOperand(const StaticInst *si, int idx) override 179 { 180 numFpRegReads++; | 180 } 181 182 /** Reads a floating point register of single register width. */ 183 FloatReg readFloatRegOperand(const StaticInst *si, int idx) override 184 { 185 numFpRegReads++; |
181 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; 182 return thread->readFloatReg(reg_idx); | 186 RegId reg = si->srcRegIdx(idx); 187 assert(reg.regClass == FloatRegClass); 188 return thread->readFloatReg(reg.regIdx); |
183 } 184 185 /** Reads a floating point register in its binary format, instead 186 * of by value. */ 187 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) override 188 { 189 numFpRegReads++; | 189 } 190 191 /** Reads a floating point register in its binary format, instead 192 * of by value. */ 193 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) override 194 { 195 numFpRegReads++; |
190 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base; 191 return thread->readFloatRegBits(reg_idx); | 196 RegId reg = si->srcRegIdx(idx); 197 assert(reg.regClass == FloatRegClass); 198 return thread->readFloatRegBits(reg.regIdx); |
192 } 193 194 /** Sets a floating point register of single width to a value. */ 195 void setFloatRegOperand(const StaticInst *si, int idx, 196 FloatReg val) override 197 { 198 numFpRegWrites++; | 199 } 200 201 /** Sets a floating point register of single width to a value. */ 202 void setFloatRegOperand(const StaticInst *si, int idx, 203 FloatReg val) override 204 { 205 numFpRegWrites++; |
199 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; 200 thread->setFloatReg(reg_idx, val); | 206 RegId reg = si->destRegIdx(idx); 207 assert(reg.regClass == FloatRegClass); 208 thread->setFloatReg(reg.regIdx, val); |
201 } 202 203 /** Sets the bits of a floating point register of single width 204 * to a binary value. */ 205 void setFloatRegOperandBits(const StaticInst *si, int idx, 206 FloatRegBits val) override 207 { 208 numFpRegWrites++; | 209 } 210 211 /** Sets the bits of a floating point register of single width 212 * to a binary value. */ 213 void setFloatRegOperandBits(const StaticInst *si, int idx, 214 FloatRegBits val) override 215 { 216 numFpRegWrites++; |
209 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base; 210 thread->setFloatRegBits(reg_idx, val); | 217 RegId reg = si->destRegIdx(idx); 218 assert(reg.regClass == FloatRegClass); 219 thread->setFloatRegBits(reg.regIdx, val); |
211 } 212 213 CCReg readCCRegOperand(const StaticInst *si, int idx) override 214 { 215 numCCRegReads++; | 220 } 221 222 CCReg readCCRegOperand(const StaticInst *si, int idx) override 223 { 224 numCCRegReads++; |
216 int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base; 217 return thread->readCCReg(reg_idx); | 225 RegId reg = si->srcRegIdx(idx); 226 assert(reg.regClass == CCRegClass); 227 return thread->readCCReg(reg.regIdx); |
218 } 219 220 void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override 221 { 222 numCCRegWrites++; | 228 } 229 230 void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override 231 { 232 numCCRegWrites++; |
223 int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base; 224 thread->setCCReg(reg_idx, val); | 233 RegId reg = si->destRegIdx(idx); 234 assert(reg.regClass == CCRegClass); 235 thread->setCCReg(reg.regIdx, val); |
225 } 226 227 MiscReg readMiscRegOperand(const StaticInst *si, int idx) override 228 { 229 numIntRegReads++; | 236 } 237 238 MiscReg readMiscRegOperand(const StaticInst *si, int idx) override 239 { 240 numIntRegReads++; |
230 int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base; 231 return thread->readMiscReg(reg_idx); | 241 RegId reg = si->srcRegIdx(idx); 242 assert(reg.regClass == MiscRegClass); 243 return thread->readMiscReg(reg.regIdx); |
232 } 233 234 void setMiscRegOperand(const StaticInst *si, int idx, 235 const MiscReg &val) override 236 { 237 numIntRegWrites++; | 244 } 245 246 void setMiscRegOperand(const StaticInst *si, int idx, 247 const MiscReg &val) override 248 { 249 numIntRegWrites++; |
238 int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base; 239 thread->setMiscReg(reg_idx, val); | 250 RegId reg = si->destRegIdx(idx); 251 assert(reg.regClass == MiscRegClass); 252 thread->setMiscReg(reg.regIdx, val); |
240 } 241 242 /** 243 * Reads a miscellaneous register, handling any architectural 244 * side effects due to reading that register. 245 */ 246 MiscReg readMiscReg(int misc_reg) override 247 { --- 145 unchanged lines hidden (view full) --- 393 } 394 395 AddressMonitor *getAddrMonitor() override 396 { 397 return cpu->getCpuAddrMonitor(thread->threadId()); 398 } 399 400#if THE_ISA == MIPS_ISA | 253 } 254 255 /** 256 * Reads a miscellaneous register, handling any architectural 257 * side effects due to reading that register. 258 */ 259 MiscReg readMiscReg(int misc_reg) override 260 { --- 145 unchanged lines hidden (view full) --- 406 } 407 408 AddressMonitor *getAddrMonitor() override 409 { 410 return cpu->getCpuAddrMonitor(thread->threadId()); 411 } 412 413#if THE_ISA == MIPS_ISA |
401 MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID) | 414 MiscReg readRegOtherThread(RegId reg, ThreadID tid = InvalidThreadID) |
402 override 403 { 404 panic("Simple CPU models do not support multithreaded " 405 "register access."); 406 } 407 | 415 override 416 { 417 panic("Simple CPU models do not support multithreaded " 418 "register access."); 419 } 420 |
408 void setRegOtherThread(int regIdx, MiscReg val, | 421 void setRegOtherThread(RegId reg, MiscReg val, |
409 ThreadID tid = InvalidThreadID) override 410 { 411 panic("Simple CPU models do not support multithreaded " 412 "register access."); 413 } 414 415#endif 416 417}; 418 419#endif // __CPU_EXEC_CONTEXT_HH__ | 422 ThreadID tid = InvalidThreadID) override 423 { 424 panic("Simple CPU models do not support multithreaded " 425 "register access."); 426 } 427 428#endif 429 430}; 431 432#endif // __CPU_EXEC_CONTEXT_HH__ |