exec_context.hh (11148:1bc3d93c7eaa) exec_context.hh (11168:f98eb2da15a4)
1/*
2 * Copyright (c) 2014-2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 146 unchanged lines hidden (view full) ---

155 public:
156 /** Constructor */
157 SimpleExecContext(BaseSimpleCPU* _cpu, SimpleThread* _thread)
158 : cpu(_cpu), thread(_thread), fetchOffset(0), stayAtPC(false),
159 numInst(0), numOp(0), numLoad(0), lastIcacheStall(0), lastDcacheStall(0)
160 { }
161
162 /** Reads an integer register. */
1/*
2 * Copyright (c) 2014-2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 146 unchanged lines hidden (view full) ---

155 public:
156 /** Constructor */
157 SimpleExecContext(BaseSimpleCPU* _cpu, SimpleThread* _thread)
158 : cpu(_cpu), thread(_thread), fetchOffset(0), stayAtPC(false),
159 numInst(0), numOp(0), numLoad(0), lastIcacheStall(0), lastDcacheStall(0)
160 { }
161
162 /** Reads an integer register. */
163 IntReg readIntRegOperand(const StaticInst *si, int idx) M5_ATTR_OVERRIDE
163 IntReg readIntRegOperand(const StaticInst *si, int idx) override
164 {
165 numIntRegReads++;
166 return thread->readIntReg(si->srcRegIdx(idx));
167 }
168
169 /** Sets an integer register to a value. */
164 {
165 numIntRegReads++;
166 return thread->readIntReg(si->srcRegIdx(idx));
167 }
168
169 /** Sets an integer register to a value. */
170 void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
171 M5_ATTR_OVERRIDE
170 void setIntRegOperand(const StaticInst *si, int idx, IntReg val) override
172 {
173 numIntRegWrites++;
174 thread->setIntReg(si->destRegIdx(idx), val);
175 }
176
177 /** Reads a floating point register of single register width. */
171 {
172 numIntRegWrites++;
173 thread->setIntReg(si->destRegIdx(idx), val);
174 }
175
176 /** Reads a floating point register of single register width. */
178 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
179 M5_ATTR_OVERRIDE
177 FloatReg readFloatRegOperand(const StaticInst *si, int idx) override
180 {
181 numFpRegReads++;
182 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
183 return thread->readFloatReg(reg_idx);
184 }
185
186 /** Reads a floating point register in its binary format, instead
187 * of by value. */
178 {
179 numFpRegReads++;
180 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
181 return thread->readFloatReg(reg_idx);
182 }
183
184 /** Reads a floating point register in its binary format, instead
185 * of by value. */
188 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
189 M5_ATTR_OVERRIDE
186 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) override
190 {
191 numFpRegReads++;
192 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
193 return thread->readFloatRegBits(reg_idx);
194 }
195
196 /** Sets a floating point register of single width to a value. */
187 {
188 numFpRegReads++;
189 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
190 return thread->readFloatRegBits(reg_idx);
191 }
192
193 /** Sets a floating point register of single width to a value. */
197 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
198 M5_ATTR_OVERRIDE
194 void setFloatRegOperand(const StaticInst *si, int idx,
195 FloatReg val) override
199 {
200 numFpRegWrites++;
201 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
202 thread->setFloatReg(reg_idx, val);
203 }
204
205 /** Sets the bits of a floating point register of single width
206 * to a binary value. */
207 void setFloatRegOperandBits(const StaticInst *si, int idx,
196 {
197 numFpRegWrites++;
198 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
199 thread->setFloatReg(reg_idx, val);
200 }
201
202 /** Sets the bits of a floating point register of single width
203 * to a binary value. */
204 void setFloatRegOperandBits(const StaticInst *si, int idx,
208 FloatRegBits val) M5_ATTR_OVERRIDE
205 FloatRegBits val) override
209 {
210 numFpRegWrites++;
211 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
212 thread->setFloatRegBits(reg_idx, val);
213 }
214
206 {
207 numFpRegWrites++;
208 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
209 thread->setFloatRegBits(reg_idx, val);
210 }
211
215 CCReg readCCRegOperand(const StaticInst *si, int idx) M5_ATTR_OVERRIDE
212 CCReg readCCRegOperand(const StaticInst *si, int idx) override
216 {
217 numCCRegReads++;
218 int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
219 return thread->readCCReg(reg_idx);
220 }
221
213 {
214 numCCRegReads++;
215 int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
216 return thread->readCCReg(reg_idx);
217 }
218
222 void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
223 M5_ATTR_OVERRIDE
219 void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
224 {
225 numCCRegWrites++;
226 int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
227 thread->setCCReg(reg_idx, val);
228 }
229
220 {
221 numCCRegWrites++;
222 int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
223 thread->setCCReg(reg_idx, val);
224 }
225
230 MiscReg readMiscRegOperand(const StaticInst *si, int idx) M5_ATTR_OVERRIDE
226 MiscReg readMiscRegOperand(const StaticInst *si, int idx) override
231 {
232 numIntRegReads++;
233 int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
234 return thread->readMiscReg(reg_idx);
235 }
236
227 {
228 numIntRegReads++;
229 int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
230 return thread->readMiscReg(reg_idx);
231 }
232
237 void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val)
238 M5_ATTR_OVERRIDE
233 void setMiscRegOperand(const StaticInst *si, int idx,
234 const MiscReg &val) override
239 {
240 numIntRegWrites++;
241 int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
242 thread->setMiscReg(reg_idx, val);
243 }
244
245 /**
246 * Reads a miscellaneous register, handling any architectural
247 * side effects due to reading that register.
248 */
235 {
236 numIntRegWrites++;
237 int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
238 thread->setMiscReg(reg_idx, val);
239 }
240
241 /**
242 * Reads a miscellaneous register, handling any architectural
243 * side effects due to reading that register.
244 */
249 MiscReg readMiscReg(int misc_reg) M5_ATTR_OVERRIDE
245 MiscReg readMiscReg(int misc_reg) override
250 {
251 numIntRegReads++;
252 return thread->readMiscReg(misc_reg);
253 }
254
255 /**
256 * Sets a miscellaneous register, handling any architectural
257 * side effects due to writing that register.
258 */
246 {
247 numIntRegReads++;
248 return thread->readMiscReg(misc_reg);
249 }
250
251 /**
252 * Sets a miscellaneous register, handling any architectural
253 * side effects due to writing that register.
254 */
259 void setMiscReg(int misc_reg, const MiscReg &val) M5_ATTR_OVERRIDE
255 void setMiscReg(int misc_reg, const MiscReg &val) override
260 {
261 numIntRegWrites++;
262 thread->setMiscReg(misc_reg, val);
263 }
264
256 {
257 numIntRegWrites++;
258 thread->setMiscReg(misc_reg, val);
259 }
260
265 PCState pcState() const M5_ATTR_OVERRIDE
261 PCState pcState() const override
266 {
267 return thread->pcState();
268 }
269
262 {
263 return thread->pcState();
264 }
265
270 void pcState(const PCState &val) M5_ATTR_OVERRIDE
266 void pcState(const PCState &val) override
271 {
272 thread->pcState(val);
273 }
274
275
276 /**
277 * Record the effective address of the instruction.
278 *
279 * @note Only valid for memory ops.
280 */
267 {
268 thread->pcState(val);
269 }
270
271
272 /**
273 * Record the effective address of the instruction.
274 *
275 * @note Only valid for memory ops.
276 */
281 void setEA(Addr EA) M5_ATTR_OVERRIDE
277 void setEA(Addr EA) override
282 { panic("BaseSimpleCPU::setEA() not implemented\n"); }
283
284 /**
285 * Get the effective address of the instruction.
286 *
287 * @note Only valid for memory ops.
288 */
278 { panic("BaseSimpleCPU::setEA() not implemented\n"); }
279
280 /**
281 * Get the effective address of the instruction.
282 *
283 * @note Only valid for memory ops.
284 */
289 Addr getEA() const M5_ATTR_OVERRIDE
285 Addr getEA() const override
290 { panic("BaseSimpleCPU::getEA() not implemented\n"); }
291
292 Fault readMem(Addr addr, uint8_t *data, unsigned int size,
286 { panic("BaseSimpleCPU::getEA() not implemented\n"); }
287
288 Fault readMem(Addr addr, uint8_t *data, unsigned int size,
293 unsigned int flags) M5_ATTR_OVERRIDE
289 unsigned int flags) override
294 {
295 return cpu->readMem(addr, data, size, flags);
296 }
297
298 Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
290 {
291 return cpu->readMem(addr, data, size, flags);
292 }
293
294 Fault writeMem(uint8_t *data, unsigned int size, Addr addr,
299 unsigned int flags, uint64_t *res) M5_ATTR_OVERRIDE
295 unsigned int flags, uint64_t *res) override
300 {
301 return cpu->writeMem(data, size, addr, flags, res);
302 }
303
304 /**
305 * Sets the number of consecutive store conditional failures.
306 */
296 {
297 return cpu->writeMem(data, size, addr, flags, res);
298 }
299
300 /**
301 * Sets the number of consecutive store conditional failures.
302 */
307 void setStCondFailures(unsigned int sc_failures) M5_ATTR_OVERRIDE
303 void setStCondFailures(unsigned int sc_failures) override
308 {
309 thread->setStCondFailures(sc_failures);
310 }
311
312 /**
313 * Returns the number of consecutive store conditional failures.
314 */
304 {
305 thread->setStCondFailures(sc_failures);
306 }
307
308 /**
309 * Returns the number of consecutive store conditional failures.
310 */
315 unsigned int readStCondFailures() const M5_ATTR_OVERRIDE
311 unsigned int readStCondFailures() const override
316 {
317 return thread->readStCondFailures();
318 }
319
320 /**
321 * Executes a syscall specified by the callnum.
322 */
312 {
313 return thread->readStCondFailures();
314 }
315
316 /**
317 * Executes a syscall specified by the callnum.
318 */
323 void syscall(int64_t callnum) M5_ATTR_OVERRIDE
319 void syscall(int64_t callnum) override
324 {
325 if (FullSystem)
326 panic("Syscall emulation isn't available in FS mode.");
327
328 thread->syscall(callnum);
329 }
330
331 /** Returns a pointer to the ThreadContext. */
320 {
321 if (FullSystem)
322 panic("Syscall emulation isn't available in FS mode.");
323
324 thread->syscall(callnum);
325 }
326
327 /** Returns a pointer to the ThreadContext. */
332 ThreadContext *tcBase() M5_ATTR_OVERRIDE
328 ThreadContext *tcBase() override
333 {
334 return thread->getTC();
335 }
336
337 /**
338 * Somewhat Alpha-specific function that handles returning from an
339 * error or interrupt.
340 */
329 {
330 return thread->getTC();
331 }
332
333 /**
334 * Somewhat Alpha-specific function that handles returning from an
335 * error or interrupt.
336 */
341 Fault hwrei() M5_ATTR_OVERRIDE
337 Fault hwrei() override
342 {
343 return thread->hwrei();
344 }
345
346 /**
347 * Check for special simulator handling of specific PAL calls. If
348 * return value is false, actual PAL call will be suppressed.
349 */
338 {
339 return thread->hwrei();
340 }
341
342 /**
343 * Check for special simulator handling of specific PAL calls. If
344 * return value is false, actual PAL call will be suppressed.
345 */
350 bool simPalCheck(int palFunc) M5_ATTR_OVERRIDE
346 bool simPalCheck(int palFunc) override
351 {
352 return thread->simPalCheck(palFunc);
353 }
354
347 {
348 return thread->simPalCheck(palFunc);
349 }
350
355 bool readPredicate() M5_ATTR_OVERRIDE
351 bool readPredicate() override
356 {
357 return thread->readPredicate();
358 }
359
352 {
353 return thread->readPredicate();
354 }
355
360 void setPredicate(bool val) M5_ATTR_OVERRIDE
356 void setPredicate(bool val) override
361 {
362 thread->setPredicate(val);
363
364 if (cpu->traceData) {
365 cpu->traceData->setPredicate(val);
366 }
367 }
368
369 /**
370 * Invalidate a page in the DTLB <i>and</i> ITLB.
371 */
357 {
358 thread->setPredicate(val);
359
360 if (cpu->traceData) {
361 cpu->traceData->setPredicate(val);
362 }
363 }
364
365 /**
366 * Invalidate a page in the DTLB <i>and</i> ITLB.
367 */
372 void demapPage(Addr vaddr, uint64_t asn) M5_ATTR_OVERRIDE
368 void demapPage(Addr vaddr, uint64_t asn) override
373 {
374 thread->demapPage(vaddr, asn);
375 }
376
369 {
370 thread->demapPage(vaddr, asn);
371 }
372
377 void armMonitor(Addr address) M5_ATTR_OVERRIDE
373 void armMonitor(Addr address) override
378 {
379 cpu->armMonitor(thread->threadId(), address);
380 }
381
374 {
375 cpu->armMonitor(thread->threadId(), address);
376 }
377
382 bool mwait(PacketPtr pkt) M5_ATTR_OVERRIDE
378 bool mwait(PacketPtr pkt) override
383 {
384 return cpu->mwait(thread->threadId(), pkt);
385 }
386
379 {
380 return cpu->mwait(thread->threadId(), pkt);
381 }
382
387 void mwaitAtomic(ThreadContext *tc) M5_ATTR_OVERRIDE
383 void mwaitAtomic(ThreadContext *tc) override
388 {
389 cpu->mwaitAtomic(thread->threadId(), tc, thread->dtb);
390 }
391
384 {
385 cpu->mwaitAtomic(thread->threadId(), tc, thread->dtb);
386 }
387
392 AddressMonitor *getAddrMonitor() M5_ATTR_OVERRIDE
388 AddressMonitor *getAddrMonitor() override
393 {
394 return cpu->getCpuAddrMonitor(thread->threadId());
395 }
396
397#if THE_ISA == MIPS_ISA
398 MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID)
389 {
390 return cpu->getCpuAddrMonitor(thread->threadId());
391 }
392
393#if THE_ISA == MIPS_ISA
394 MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID)
399 M5_ATTR_OVERRIDE
395 override
400 {
401 panic("Simple CPU models do not support multithreaded "
402 "register access.");
403 }
404
405 void setRegOtherThread(int regIdx, MiscReg val,
396 {
397 panic("Simple CPU models do not support multithreaded "
398 "register access.");
399 }
400
401 void setRegOtherThread(int regIdx, MiscReg val,
406 ThreadID tid = InvalidThreadID) M5_ATTR_OVERRIDE
402 ThreadID tid = InvalidThreadID) override
407 {
408 panic("Simple CPU models do not support multithreaded "
409 "register access.");
410 }
411
412#endif
413
414};
415
416#endif // __CPU_EXEC_CONTEXT_HH__
403 {
404 panic("Simple CPU models do not support multithreaded "
405 "register access.");
406 }
407
408#endif
409
410};
411
412#endif // __CPU_EXEC_CONTEXT_HH__