exec_context.hh (11147:cc8d6e99cf46) exec_context.hh (11148:1bc3d93c7eaa)
1/*
2 * Copyright (c) 2014-2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 362 unchanged lines hidden (view full) ---

371 */
372 void demapPage(Addr vaddr, uint64_t asn) M5_ATTR_OVERRIDE
373 {
374 thread->demapPage(vaddr, asn);
375 }
376
377 void armMonitor(Addr address) M5_ATTR_OVERRIDE
378 {
1/*
2 * Copyright (c) 2014-2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 362 unchanged lines hidden (view full) ---

371 */
372 void demapPage(Addr vaddr, uint64_t asn) M5_ATTR_OVERRIDE
373 {
374 thread->demapPage(vaddr, asn);
375 }
376
377 void armMonitor(Addr address) M5_ATTR_OVERRIDE
378 {
379 cpu->armMonitor(address);
379 cpu->armMonitor(thread->threadId(), address);
380 }
381
382 bool mwait(PacketPtr pkt) M5_ATTR_OVERRIDE
383 {
380 }
381
382 bool mwait(PacketPtr pkt) M5_ATTR_OVERRIDE
383 {
384 return cpu->mwait(pkt);
384 return cpu->mwait(thread->threadId(), pkt);
385 }
386
387 void mwaitAtomic(ThreadContext *tc) M5_ATTR_OVERRIDE
388 {
385 }
386
387 void mwaitAtomic(ThreadContext *tc) M5_ATTR_OVERRIDE
388 {
389 cpu->mwaitAtomic(tc, thread->dtb);
389 cpu->mwaitAtomic(thread->threadId(), tc, thread->dtb);
390 }
391
392 AddressMonitor *getAddrMonitor() M5_ATTR_OVERRIDE
393 {
390 }
391
392 AddressMonitor *getAddrMonitor() M5_ATTR_OVERRIDE
393 {
394 return cpu->getCpuAddrMonitor();
394 return cpu->getCpuAddrMonitor(thread->threadId());
395 }
396
397#if THE_ISA == MIPS_ISA
398 MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID)
399 M5_ATTR_OVERRIDE
400 {
401 panic("Simple CPU models do not support multithreaded "
402 "register access.");

--- 14 unchanged lines hidden --- 		395 }
396
397#if THE_ISA == MIPS_ISA
398 MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID)
399 M5_ATTR_OVERRIDE
400 {
401 panic("Simple CPU models do not support multithreaded "
402 "register access.");

--- 14 unchanged lines hidden ---