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< * Copyright (c) 2014-2016 ARM Limited
---
> * Copyright (c) 2014-2017 ARM Limited
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> // Number of predicate register file accesses
> mutable Stats::Scalar numVecPredRegReads;
> Stats::Scalar numVecPredRegWrites;
>
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> const VecPredRegContainer&
> readVecPredRegOperand(const StaticInst *si, int idx) const override
> {
> numVecPredRegReads++;
> const RegId& reg = si->srcRegIdx(idx);
> assert(reg.isVecPredReg());
> return thread->readVecPredReg(reg);
> }
>
> VecPredRegContainer&
> getWritableVecPredRegOperand(const StaticInst *si, int idx) override
> {
> numVecPredRegWrites++;
> const RegId& reg = si->destRegIdx(idx);
> assert(reg.isVecPredReg());
> return thread->getWritableVecPredReg(reg);
> }
>
> void
> setVecPredRegOperand(const StaticInst *si, int idx,
> const VecPredRegContainer& val) override
> {
> numVecPredRegWrites++;
> const RegId& reg = si->destRegIdx(idx);
> assert(reg.isVecPredReg());
> thread->setVecPredReg(reg, val);
> }
>