168,170c168,170
< RegId reg = si->srcRegIdx(idx);
< assert(reg.regClass == IntRegClass);
< return thread->readIntReg(reg.regIdx);
---
> const RegId& reg = si->srcRegIdx(idx);
> assert(reg.isIntReg());
> return thread->readIntReg(reg.index());
177,179c177,179
< RegId reg = si->destRegIdx(idx);
< assert(reg.regClass == IntRegClass);
< thread->setIntReg(reg.regIdx, val);
---
> const RegId& reg = si->destRegIdx(idx);
> assert(reg.isIntReg());
> thread->setIntReg(reg.index(), val);
186,188c186,188
< RegId reg = si->srcRegIdx(idx);
< assert(reg.regClass == FloatRegClass);
< return thread->readFloatReg(reg.regIdx);
---
> const RegId& reg = si->srcRegIdx(idx);
> assert(reg.isFloatReg());
> return thread->readFloatReg(reg.index());
196,198c196,198
< RegId reg = si->srcRegIdx(idx);
< assert(reg.regClass == FloatRegClass);
< return thread->readFloatRegBits(reg.regIdx);
---
> const RegId& reg = si->srcRegIdx(idx);
> assert(reg.isFloatReg());
> return thread->readFloatRegBits(reg.index());
206,208c206,208
< RegId reg = si->destRegIdx(idx);
< assert(reg.regClass == FloatRegClass);
< thread->setFloatReg(reg.regIdx, val);
---
> const RegId& reg = si->destRegIdx(idx);
> assert(reg.isFloatReg());
> thread->setFloatReg(reg.index(), val);
217,219c217,219
< RegId reg = si->destRegIdx(idx);
< assert(reg.regClass == FloatRegClass);
< thread->setFloatRegBits(reg.regIdx, val);
---
> const RegId& reg = si->destRegIdx(idx);
> assert(reg.isFloatReg());
> thread->setFloatRegBits(reg.index(), val);
225,227c225,227
< RegId reg = si->srcRegIdx(idx);
< assert(reg.regClass == CCRegClass);
< return thread->readCCReg(reg.regIdx);
---
> const RegId& reg = si->srcRegIdx(idx);
> assert(reg.isCCReg());
> return thread->readCCReg(reg.index());
233,235c233,235
< RegId reg = si->destRegIdx(idx);
< assert(reg.regClass == CCRegClass);
< thread->setCCReg(reg.regIdx, val);
---
> const RegId& reg = si->destRegIdx(idx);
> assert(reg.isCCReg());
> thread->setCCReg(reg.index(), val);
241,243c241,243
< RegId reg = si->srcRegIdx(idx);
< assert(reg.regClass == MiscRegClass);
< return thread->readMiscReg(reg.regIdx);
---
> const RegId& reg = si->srcRegIdx(idx);
> assert(reg.isMiscReg());
> return thread->readMiscReg(reg.index());
250,252c250,252
< RegId reg = si->destRegIdx(idx);
< assert(reg.regClass == MiscRegClass);
< thread->setMiscReg(reg.regIdx, val);
---
> const RegId& reg = si->destRegIdx(idx);
> assert(reg.isMiscReg());
> thread->setMiscReg(reg.index(), val);
414c414,415
< MiscReg readRegOtherThread(RegId reg, ThreadID tid = InvalidThreadID)
---
> MiscReg readRegOtherThread(const RegId& reg,
> ThreadID tid = InvalidThreadID)
421c422
< void setRegOtherThread(RegId reg, MiscReg val,
---
> void setRegOtherThread(const RegId& reg, MiscReg val,