1/*
2 * Copyright (c) 2014-2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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116 // Number of float register file accesses
117 Stats::Scalar numFpRegReads;
118 Stats::Scalar numFpRegWrites;
119
120 // Number of vector register file accesses
121 mutable Stats::Scalar numVecRegReads;
122 Stats::Scalar numVecRegWrites;
123
124 // Number of condition code register file accesses
125 Stats::Scalar numCCRegReads;
126 Stats::Scalar numCCRegWrites;
127
128 // Number of simulated memory references
129 Stats::Scalar numMemRefs;
130 Stats::Scalar numLoadInsts;
131 Stats::Scalar numStoreInsts;

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328 const VecElem val) override
329 {
330 numVecRegWrites++;
331 const RegId& reg = si->destRegIdx(idx);
332 assert(reg.isVecElem());
333 thread->setVecElem(reg, val);
334 }
335
336 CCReg
337 readCCRegOperand(const StaticInst *si, int idx) override
338 {
339 numCCRegReads++;
340 const RegId& reg = si->srcRegIdx(idx);
341 assert(reg.isCCReg());
342 return thread->readCCReg(reg.index());
343 }

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