1/*
2 * Copyright (c) 2014-2015 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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160 : cpu(_cpu), thread(_thread), fetchOffset(0), stayAtPC(false),
161 numInst(0), numOp(0), numLoad(0), lastIcacheStall(0), lastDcacheStall(0)
162 { }
163
164 /** Reads an integer register. */
165 IntReg readIntRegOperand(const StaticInst *si, int idx) override
166 {
167 numIntRegReads++;
168 RegId reg = si->srcRegIdx(idx);
169 assert(reg.regClass == IntRegClass);
170 return thread->readIntReg(reg.regIdx);
171 }
172
173 /** Sets an integer register to a value. */
174 void setIntRegOperand(const StaticInst *si, int idx, IntReg val) override
175 {
176 numIntRegWrites++;
177 RegId reg = si->destRegIdx(idx);
178 assert(reg.regClass == IntRegClass);
179 thread->setIntReg(reg.regIdx, val);
180 }
181
182 /** Reads a floating point register of single register width. */
183 FloatReg readFloatRegOperand(const StaticInst *si, int idx) override
184 {
185 numFpRegReads++;
186 RegId reg = si->srcRegIdx(idx);
187 assert(reg.regClass == FloatRegClass);
188 return thread->readFloatReg(reg.regIdx);
189 }
190
191 /** Reads a floating point register in its binary format, instead
192 * of by value. */
193 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) override
194 {
195 numFpRegReads++;
196 RegId reg = si->srcRegIdx(idx);
197 assert(reg.regClass == FloatRegClass);
198 return thread->readFloatRegBits(reg.regIdx);
199 }
200
201 /** Sets a floating point register of single width to a value. */
202 void setFloatRegOperand(const StaticInst *si, int idx,
203 FloatReg val) override
204 {
205 numFpRegWrites++;
206 RegId reg = si->destRegIdx(idx);
207 assert(reg.regClass == FloatRegClass);
208 thread->setFloatReg(reg.regIdx, val);
209 }
210
211 /** Sets the bits of a floating point register of single width
212 * to a binary value. */
213 void setFloatRegOperandBits(const StaticInst *si, int idx,
214 FloatRegBits val) override
215 {
216 numFpRegWrites++;
217 RegId reg = si->destRegIdx(idx);
218 assert(reg.regClass == FloatRegClass);
219 thread->setFloatRegBits(reg.regIdx, val);
220 }
221
222 CCReg readCCRegOperand(const StaticInst *si, int idx) override
223 {
224 numCCRegReads++;
225 RegId reg = si->srcRegIdx(idx);
226 assert(reg.regClass == CCRegClass);
227 return thread->readCCReg(reg.regIdx);
228 }
229
230 void setCCRegOperand(const StaticInst *si, int idx, CCReg val) override
231 {
232 numCCRegWrites++;
233 RegId reg = si->destRegIdx(idx);
234 assert(reg.regClass == CCRegClass);
235 thread->setCCReg(reg.regIdx, val);
236 }
237
238 MiscReg readMiscRegOperand(const StaticInst *si, int idx) override
239 {
240 numIntRegReads++;
241 RegId reg = si->srcRegIdx(idx);
242 assert(reg.regClass == MiscRegClass);
243 return thread->readMiscReg(reg.regIdx);
244 }
245
246 void setMiscRegOperand(const StaticInst *si, int idx,
247 const MiscReg &val) override
248 {
249 numIntRegWrites++;
250 RegId reg = si->destRegIdx(idx);
251 assert(reg.regClass == MiscRegClass);
252 thread->setMiscReg(reg.regIdx, val);
253 }
254
255 /**
256 * Reads a miscellaneous register, handling any architectural
257 * side effects due to reading that register.
258 */
259 MiscReg readMiscReg(int misc_reg) override
260 {

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406 }
407
408 AddressMonitor *getAddrMonitor() override
409 {
410 return cpu->getCpuAddrMonitor(thread->threadId());
411 }
412
413#if THE_ISA == MIPS_ISA
414 MiscReg readRegOtherThread(RegId reg, ThreadID tid = InvalidThreadID)
415 override
416 {
417 panic("Simple CPU models do not support multithreaded "
418 "register access.");
419 }
420
421 void setRegOtherThread(RegId reg, MiscReg val,
422 ThreadID tid = InvalidThreadID) override
423 {
424 panic("Simple CPU models do not support multithreaded "
425 "register access.");
426 }
427
428#endif
429
430};
431
432#endif // __CPU_EXEC_CONTEXT_HH__