base.hh (9920:028e4da64b42) base.hh (10061:3b0d0c988ed6)
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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72 class ITB;
73}
74
75namespace Trace {
76 class InstRecord;
77}
78
79struct BaseSimpleCPUParams;
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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72 class ITB;
73}
74
75namespace Trace {
76 class InstRecord;
77}
78
79struct BaseSimpleCPUParams;
80class BPredUnit;
80
81
81
82class BaseSimpleCPU : public BaseCPU
83{
84 protected:
85 typedef TheISA::MiscReg MiscReg;
86 typedef TheISA::FloatReg FloatReg;
87 typedef TheISA::FloatRegBits FloatRegBits;
88 typedef TheISA::CCReg CCReg;
89
82class BaseSimpleCPU : public BaseCPU
83{
84 protected:
85 typedef TheISA::MiscReg MiscReg;
86 typedef TheISA::FloatReg FloatReg;
87 typedef TheISA::FloatRegBits FloatRegBits;
88 typedef TheISA::CCReg CCReg;
89
90 BPredUnit *branchPred;
91
90 protected:
91 Trace::InstRecord *traceData;
92
93 inline void checkPcEventQueue() {
94 Addr oldpc, pc = thread->instAddr();
95 do {
96 oldpc = pc;
97 system->pcEventQueue.service(tc);

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267 // number of cycles stalled for D-cache responses
268 Stats::Scalar dcacheStallCycles;
269 Counter lastDcacheStall;
270
271 // number of cycles stalled for D-cache retries
272 Stats::Scalar dcacheRetryCycles;
273 Counter lastDcacheRetry;
274
92 protected:
93 Trace::InstRecord *traceData;
94
95 inline void checkPcEventQueue() {
96 Addr oldpc, pc = thread->instAddr();
97 do {
98 oldpc = pc;
99 system->pcEventQueue.service(tc);

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269 // number of cycles stalled for D-cache responses
270 Stats::Scalar dcacheStallCycles;
271 Counter lastDcacheStall;
272
273 // number of cycles stalled for D-cache retries
274 Stats::Scalar dcacheRetryCycles;
275 Counter lastDcacheRetry;
276
277 /// @{
278 /// Total number of branches fetched
279 Stats::Scalar numBranches;
280 /// Number of branches predicted as taken
281 Stats::Scalar numPredictedBranches;
282 /// Number of misprediced branches
283 Stats::Scalar numBranchMispred;
284 /// @}
285
275 void serializeThread(std::ostream &os, ThreadID tid);
276 void unserializeThread(Checkpoint *cp, const std::string &section,
277 ThreadID tid);
278
279 // These functions are only used in CPU models that split
280 // effective address computation from the actual memory access.
281 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
282 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n");

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441 if (FullSystem)
442 panic("Syscall emulation isn't available in FS mode.\n");
443
444 thread->syscall(callnum);
445 }
446
447 bool misspeculating() { return thread->misspeculating(); }
448 ThreadContext *tcBase() { return tc; }
286 void serializeThread(std::ostream &os, ThreadID tid);
287 void unserializeThread(Checkpoint *cp, const std::string &section,
288 ThreadID tid);
289
290 // These functions are only used in CPU models that split
291 // effective address computation from the actual memory access.
292 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
293 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n");

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452 if (FullSystem)
453 panic("Syscall emulation isn't available in FS mode.\n");
454
455 thread->syscall(callnum);
456 }
457
458 bool misspeculating() { return thread->misspeculating(); }
459 ThreadContext *tcBase() { return tc; }
460
461 private:
462 TheISA::PCState pred_pc;
449};
450
451#endif // __CPU_SIMPLE_BASE_HH__
463};
464
465#endif // __CPU_SIMPLE_BASE_HH__