base.hh (9918:2c7219e2d999) base.hh (9920:028e4da64b42)
1/*
2 * Copyright (c) 2011-2012 ARM Limited
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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79
80
81class BaseSimpleCPU : public BaseCPU
82{
83 protected:
84 typedef TheISA::MiscReg MiscReg;
85 typedef TheISA::FloatReg FloatReg;
86 typedef TheISA::FloatRegBits FloatRegBits;
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated

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80
81
82class BaseSimpleCPU : public BaseCPU
83{
84 protected:
85 typedef TheISA::MiscReg MiscReg;
86 typedef TheISA::FloatReg FloatReg;
87 typedef TheISA::FloatRegBits FloatRegBits;
88 typedef TheISA::CCReg CCReg;
87
88 protected:
89 Trace::InstRecord *traceData;
90
91 inline void checkPcEventQueue() {
92 Addr oldpc, pc = thread->instAddr();
93 do {
94 oldpc = pc;

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226 //number of integer register file accesses
227 Stats::Scalar numIntRegReads;
228 Stats::Scalar numIntRegWrites;
229
230 //number of float register file accesses
231 Stats::Scalar numFpRegReads;
232 Stats::Scalar numFpRegWrites;
233
89
90 protected:
91 Trace::InstRecord *traceData;
92
93 inline void checkPcEventQueue() {
94 Addr oldpc, pc = thread->instAddr();
95 do {
96 oldpc = pc;

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228 //number of integer register file accesses
229 Stats::Scalar numIntRegReads;
230 Stats::Scalar numIntRegWrites;
231
232 //number of float register file accesses
233 Stats::Scalar numFpRegReads;
234 Stats::Scalar numFpRegWrites;
235
236 //number of condition code register file accesses
237 Stats::Scalar numCCRegReads;
238 Stats::Scalar numCCRegWrites;
239
234 // number of simulated memory references
235 Stats::Scalar numMemRefs;
236 Stats::Scalar numLoadInsts;
237 Stats::Scalar numStoreInsts;
238
239 // number of idle cycles
240 Stats::Formula numIdleCycles;
241

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302
303 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
304 {
305 numFpRegReads++;
306 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
307 return thread->readFloatRegBits(reg_idx);
308 }
309
240 // number of simulated memory references
241 Stats::Scalar numMemRefs;
242 Stats::Scalar numLoadInsts;
243 Stats::Scalar numStoreInsts;
244
245 // number of idle cycles
246 Stats::Formula numIdleCycles;
247

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308
309 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
310 {
311 numFpRegReads++;
312 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
313 return thread->readFloatRegBits(reg_idx);
314 }
315
316 CCReg readCCRegOperand(const StaticInst *si, int idx)
317 {
318 numCCRegReads++;
319 int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
320 return thread->readCCReg(reg_idx);
321 }
322
310 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
311 {
312 numIntRegWrites++;
313 thread->setIntReg(si->destRegIdx(idx), val);
314 }
315
316 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
317 {

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323 void setFloatRegOperandBits(const StaticInst *si, int idx,
324 FloatRegBits val)
325 {
326 numFpRegWrites++;
327 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
328 thread->setFloatRegBits(reg_idx, val);
329 }
330
323 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
324 {
325 numIntRegWrites++;
326 thread->setIntReg(si->destRegIdx(idx), val);
327 }
328
329 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
330 {

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336 void setFloatRegOperandBits(const StaticInst *si, int idx,
337 FloatRegBits val)
338 {
339 numFpRegWrites++;
340 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
341 thread->setFloatRegBits(reg_idx, val);
342 }
343
344 void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
345 {
346 numCCRegWrites++;
347 int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
348 thread->setCCReg(reg_idx, val);
349 }
350
331 bool readPredicate() { return thread->readPredicate(); }
332 void setPredicate(bool val)
333 {
334 thread->setPredicate(val);
335 if (traceData) {
336 traceData->setPredicate(val);
337 }
338 }

--- 93 unchanged lines hidden --- 		351 bool readPredicate() { return thread->readPredicate(); }
352 void setPredicate(bool val)
353 {
354 thread->setPredicate(val);
355 if (traceData) {
356 traceData->setPredicate(val);
357 }
358 }

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