base.hh (9023:e9201a7bce59) base.hh (9448:569d1e8f74e4)
1/*
1/*
2 * Copyright (c) 2011 ARM Limited
2 * Copyright (c) 2011-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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132 ITBWaitResponse,
133 IcacheRetry,
134 IcacheWaitResponse,
135 IcacheWaitSwitch,
136 DTBWaitResponse,
137 DcacheRetry,
138 DcacheWaitResponse,
139 DcacheWaitSwitch,
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

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132 ITBWaitResponse,
133 IcacheRetry,
134 IcacheWaitResponse,
135 IcacheWaitSwitch,
136 DTBWaitResponse,
137 DcacheRetry,
138 DcacheWaitResponse,
139 DcacheWaitSwitch,
140 SwitchedOut
141 };
142
143 Status _status;
144
145 public:
146
147 Addr dbg_vtophys(Addr addr);
148

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260 // number of cycles stalled for D-cache responses
261 Stats::Scalar dcacheStallCycles;
262 Counter lastDcacheStall;
263
264 // number of cycles stalled for D-cache retries
265 Stats::Scalar dcacheRetryCycles;
266 Counter lastDcacheRetry;
267
140 };
141
142 Status _status;
143
144 public:
145
146 Addr dbg_vtophys(Addr addr);
147

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259 // number of cycles stalled for D-cache responses
260 Stats::Scalar dcacheStallCycles;
261 Counter lastDcacheStall;
262
263 // number of cycles stalled for D-cache retries
264 Stats::Scalar dcacheRetryCycles;
265 Counter lastDcacheRetry;
266
268 virtual void serialize(std::ostream &os);
269 virtual void unserialize(Checkpoint *cp, const std::string &section);
267 void serializeThread(std::ostream &os, ThreadID tid);
268 void unserializeThread(Checkpoint *cp, const std::string &section,
269 ThreadID tid);
270
271 // These functions are only used in CPU models that split
272 // effective address computation from the actual memory access.
273 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
274 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n");
275 M5_DUMMY_RETURN}
276
277 // The register accessor methods provide the index of the

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271 // These functions are only used in CPU models that split
272 // effective address computation from the actual memory access.
273 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
274 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n");
275 M5_DUMMY_RETURN}
276
277 // The register accessor methods provide the index of the

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