base.hh (8733:64a7bf8fa56c) base.hh (8737:770ccf3af571)
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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87}
88class ThreadContext;
89class Checkpoint;
90
91namespace Trace {
92 class InstRecord;
93}
94
1/*
2 * Copyright (c) 2011 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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87}
88class ThreadContext;
89class Checkpoint;
90
91namespace Trace {
92 class InstRecord;
93}
94
95class BaseSimpleCPUParams;
95struct BaseSimpleCPUParams;
96
97
98class BaseSimpleCPU : public BaseCPU
99{
100 protected:
101 typedef TheISA::MiscReg MiscReg;
102 typedef TheISA::FloatReg FloatReg;
103 typedef TheISA::FloatRegBits FloatRegBits;

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184 bool stayAtPC;
185
186 void checkForInterrupts();
187 void setupFetchRequest(Request *req);
188 void preExecute();
189 void postExecute();
190 void advancePC(Fault fault);
191
96
97
98class BaseSimpleCPU : public BaseCPU
99{
100 protected:
101 typedef TheISA::MiscReg MiscReg;
102 typedef TheISA::FloatReg FloatReg;
103 typedef TheISA::FloatRegBits FloatRegBits;

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184 bool stayAtPC;
185
186 void checkForInterrupts();
187 void setupFetchRequest(Request *req);
188 void preExecute();
189 void postExecute();
190 void advancePC(Fault fault);
191
192 virtual void deallocateContext(int thread_num);
193 virtual void haltContext(int thread_num);
192 virtual void deallocateContext(ThreadID thread_num);
193 virtual void haltContext(ThreadID thread_num);
194
195 // statistics
196 virtual void regStats();
197 virtual void resetStats();
198
199 // number of simulated instructions
200 Counter numInst;
201 Counter startNumInst;

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195 // statistics
196 virtual void regStats();
197 virtual void resetStats();
198
199 // number of simulated instructions
200 Counter numInst;
201 Counter startNumInst;

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