base.hh (7783:9b880b40ac10) base.hh (7897:d9e8b1fd1a9f)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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177 Counter numInst;
178 Counter startNumInst;
179 Stats::Scalar numInsts;
180
181 void countInst()
182 {
183 numInst++;
184 numInsts++;
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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177 Counter numInst;
178 Counter startNumInst;
179 Stats::Scalar numInsts;
180
181 void countInst()
182 {
183 numInst++;
184 numInsts++;
185
185 system->totalNumInsts++;
186 thread->funcExeInst++;
187 }
188
189 virtual Counter totalInstructions() const
190 {
191 return numInst - startNumInst;
192 }
193
186 thread->funcExeInst++;
187 }
188
189 virtual Counter totalInstructions() const
190 {
191 return numInst - startNumInst;
192 }
193
194 //number of integer alu accesses
195 Stats::Scalar numIntAluAccesses;
196
197 //number of float alu accesses
198 Stats::Scalar numFpAluAccesses;
199
200 //number of function calls/returns
201 Stats::Scalar numCallsReturns;
202
203 //conditional control instructions;
204 Stats::Scalar numCondCtrlInsts;
205
206 //number of int instructions
207 Stats::Scalar numIntInsts;
208
209 //number of float instructions
210 Stats::Scalar numFpInsts;
211
212 //number of integer register file accesses
213 Stats::Scalar numIntRegReads;
214 Stats::Scalar numIntRegWrites;
215
216 //number of float register file accesses
217 Stats::Scalar numFpRegReads;
218 Stats::Scalar numFpRegWrites;
219
194 // number of simulated memory references
195 Stats::Scalar numMemRefs;
220 // number of simulated memory references
221 Stats::Scalar numMemRefs;
222 Stats::Scalar numLoadInsts;
223 Stats::Scalar numStoreInsts;
196
224
225 // number of idle cycles
226 Stats::Formula numIdleCycles;
227
228 // number of busy cycles
229 Stats::Formula numBusyCycles;
230
197 // number of simulated loads
198 Counter numLoad;
199 Counter startNumLoad;
200
201 // number of idle cycles
202 Stats::Average notIdleFraction;
203 Stats::Formula idleFraction;
204

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235 // raw pointer to the StaticInst is provided instead of a
236 // ref-counted StaticInstPtr to redice overhead. This is fine as
237 // long as these methods don't copy the pointer into any long-term
238 // storage (which is pretty hard to imagine they would have reason
239 // to do).
240
241 uint64_t readIntRegOperand(const StaticInst *si, int idx)
242 {
231 // number of simulated loads
232 Counter numLoad;
233 Counter startNumLoad;
234
235 // number of idle cycles
236 Stats::Average notIdleFraction;
237 Stats::Formula idleFraction;
238

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269 // raw pointer to the StaticInst is provided instead of a
270 // ref-counted StaticInstPtr to redice overhead. This is fine as
271 // long as these methods don't copy the pointer into any long-term
272 // storage (which is pretty hard to imagine they would have reason
273 // to do).
274
275 uint64_t readIntRegOperand(const StaticInst *si, int idx)
276 {
277 numIntRegReads++;
243 return thread->readIntReg(si->srcRegIdx(idx));
244 }
245
246 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
247 {
278 return thread->readIntReg(si->srcRegIdx(idx));
279 }
280
281 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
282 {
283 numFpRegReads++;
248 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
249 return thread->readFloatReg(reg_idx);
250 }
251
252 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
253 {
284 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
285 return thread->readFloatReg(reg_idx);
286 }
287
288 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
289 {
290 numFpRegReads++;
254 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
255 return thread->readFloatRegBits(reg_idx);
256 }
257
258 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
259 {
291 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
292 return thread->readFloatRegBits(reg_idx);
293 }
294
295 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
296 {
297 numIntRegWrites++;
260 thread->setIntReg(si->destRegIdx(idx), val);
261 }
262
263 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
264 {
298 thread->setIntReg(si->destRegIdx(idx), val);
299 }
300
301 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
302 {
303 numFpRegWrites++;
265 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
266 thread->setFloatReg(reg_idx, val);
267 }
268
269 void setFloatRegOperandBits(const StaticInst *si, int idx,
270 FloatRegBits val)
271 {
304 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
305 thread->setFloatReg(reg_idx, val);
306 }
307
308 void setFloatRegOperandBits(const StaticInst *si, int idx,
309 FloatRegBits val)
310 {
311 numFpRegWrites++;
272 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
273 thread->setFloatRegBits(reg_idx, val);
274 }
275
276 bool readPredicate() { return thread->readPredicate(); }
277 void setPredicate(bool val)
278 {
279 thread->setPredicate(val);

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289
290 MiscReg readMiscRegNoEffect(int misc_reg)
291 {
292 return thread->readMiscRegNoEffect(misc_reg);
293 }
294
295 MiscReg readMiscReg(int misc_reg)
296 {
312 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
313 thread->setFloatRegBits(reg_idx, val);
314 }
315
316 bool readPredicate() { return thread->readPredicate(); }
317 void setPredicate(bool val)
318 {
319 thread->setPredicate(val);

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329
330 MiscReg readMiscRegNoEffect(int misc_reg)
331 {
332 return thread->readMiscRegNoEffect(misc_reg);
333 }
334
335 MiscReg readMiscReg(int misc_reg)
336 {
337 numIntRegReads++;
297 return thread->readMiscReg(misc_reg);
298 }
299
300 void setMiscReg(int misc_reg, const MiscReg &val)
301 {
338 return thread->readMiscReg(misc_reg);
339 }
340
341 void setMiscReg(int misc_reg, const MiscReg &val)
342 {
343 numIntRegWrites++;
302 return thread->setMiscReg(misc_reg, val);
303 }
304
305 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
306 {
344 return thread->setMiscReg(misc_reg, val);
345 }
346
347 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
348 {
349 numIntRegReads++;
307 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
308 return thread->readMiscReg(reg_idx);
309 }
310
311 void setMiscRegOperand(
312 const StaticInst *si, int idx, const MiscReg &val)
313 {
350 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
351 return thread->readMiscReg(reg_idx);
352 }
353
354 void setMiscRegOperand(
355 const StaticInst *si, int idx, const MiscReg &val)
356 {
357 numIntRegWrites++;
314 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
315 return thread->setMiscReg(reg_idx, val);
316 }
317
318 void demapPage(Addr vaddr, uint64_t asn)
319 {
320 thread->demapPage(vaddr, asn);
321 }

--- 46 unchanged lines hidden --- 		358 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
359 return thread->setMiscReg(reg_idx, val);
360 }
361
362 void demapPage(Addr vaddr, uint64_t asn)
363 {
364 thread->demapPage(vaddr, asn);
365 }

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