base.hh (5894:8091ac99341a) base.hh (5999:3cf8e71257e0)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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172
173 // statistics
174 virtual void regStats();
175 virtual void resetStats();
176
177 // number of simulated instructions
178 Counter numInst;
179 Counter startNumInst;
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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172
173 // statistics
174 virtual void regStats();
175 virtual void resetStats();
176
177 // number of simulated instructions
178 Counter numInst;
179 Counter startNumInst;
180 Stats::Scalar<> numInsts;
180 Stats::Scalar numInsts;
181
182 void countInst()
183 {
184 numInst++;
185 numInsts++;
186
187 thread->funcExeInst++;
188 }
189
190 virtual Counter totalInstructions() const
191 {
192 return numInst - startNumInst;
193 }
194
195 // Mask to align PCs to MachInst sized boundaries
196 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
197
198 // number of simulated memory references
181
182 void countInst()
183 {
184 numInst++;
185 numInsts++;
186
187 thread->funcExeInst++;
188 }
189
190 virtual Counter totalInstructions() const
191 {
192 return numInst - startNumInst;
193 }
194
195 // Mask to align PCs to MachInst sized boundaries
196 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
197
198 // number of simulated memory references
199 Stats::Scalar<> numMemRefs;
199 Stats::Scalar numMemRefs;
200
201 // number of simulated loads
202 Counter numLoad;
203 Counter startNumLoad;
204
205 // number of idle cycles
200
201 // number of simulated loads
202 Counter numLoad;
203 Counter startNumLoad;
204
205 // number of idle cycles
206 Stats::Average<> notIdleFraction;
206 Stats::Average notIdleFraction;
207 Stats::Formula idleFraction;
208
209 // number of cycles stalled for I-cache responses
207 Stats::Formula idleFraction;
208
209 // number of cycles stalled for I-cache responses
210 Stats::Scalar<> icacheStallCycles;
210 Stats::Scalar icacheStallCycles;
211 Counter lastIcacheStall;
212
213 // number of cycles stalled for I-cache retries
211 Counter lastIcacheStall;
212
213 // number of cycles stalled for I-cache retries
214 Stats::Scalar<> icacheRetryCycles;
214 Stats::Scalar icacheRetryCycles;
215 Counter lastIcacheRetry;
216
217 // number of cycles stalled for D-cache responses
215 Counter lastIcacheRetry;
216
217 // number of cycles stalled for D-cache responses
218 Stats::Scalar<> dcacheStallCycles;
218 Stats::Scalar dcacheStallCycles;
219 Counter lastDcacheStall;
220
221 // number of cycles stalled for D-cache retries
219 Counter lastDcacheStall;
220
221 // number of cycles stalled for D-cache retries
222 Stats::Scalar<> dcacheRetryCycles;
222 Stats::Scalar dcacheRetryCycles;
223 Counter lastDcacheRetry;
224
225 virtual void serialize(std::ostream &os);
226 virtual void unserialize(Checkpoint *cp, const std::string &section);
227
228 // These functions are only used in CPU models that split
229 // effective address computation from the actual memory access.
230 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }

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223 Counter lastDcacheRetry;
224
225 virtual void serialize(std::ostream &os);
226 virtual void unserialize(Checkpoint *cp, const std::string &section);
227
228 // These functions are only used in CPU models that split
229 // effective address computation from the actual memory access.
230 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }

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