base.hh (4564:d1fb13424616) | base.hh (4661:44458219add1) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 201 unchanged lines hidden (view full) --- 210 // need to do this... 211 } 212 213 void writeHint(Addr addr, int size, unsigned flags) 214 { 215 // need to do this... 216 } 217 | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 201 unchanged lines hidden (view full) --- 210 // need to do this... 211 } 212 213 void writeHint(Addr addr, int size, unsigned flags) 214 { 215 // need to do this... 216 } 217 |
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218 Fault copySrcTranslate(Addr src); 219 220 Fault copy(Addr dest); 221 222 // The register accessor methods provide the index of the 223 // instruction's operand (e.g., 0 or 1), not the architectural 224 // register index, to simplify the implementation of register 225 // renaming. We find the architectural register index by indexing --- 122 unchanged lines hidden (view full) --- 348 unsigned readStCondFailures() { 349 return thread->readStCondFailures(); 350 } 351 352 void setStCondFailures(unsigned sc_failures) { 353 thread->setStCondFailures(sc_failures); 354 } 355 | 219 Fault copySrcTranslate(Addr src); 220 221 Fault copy(Addr dest); 222 223 // The register accessor methods provide the index of the 224 // instruction's operand (e.g., 0 or 1), not the architectural 225 // register index, to simplify the implementation of register 226 // renaming. We find the architectural register index by indexing --- 122 unchanged lines hidden (view full) --- 349 unsigned readStCondFailures() { 350 return thread->readStCondFailures(); 351 } 352 353 void setStCondFailures(unsigned sc_failures) { 354 thread->setStCondFailures(sc_failures); 355 } 356 |
357 MiscReg readRegOtherThread(int regIdx, int tid = -1) 358 { 359 panic("Simple CPU models do not support multithreaded " 360 "register access.\n"); 361 } 362 363 void setRegOtherThread(int regIdx, const MiscReg &val, int tid = -1) 364 { 365 panic("Simple CPU models do not support multithreaded " 366 "register access.\n"); 367 } 368 |
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356#if FULL_SYSTEM 357 Fault hwrei() { return thread->hwrei(); } 358 void ev5_trap(Fault fault) { fault->invoke(tc); } 359 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 360#else 361 void syscall(int64_t callnum) { thread->syscall(callnum); } 362#endif 363 364 bool misspeculating() { return thread->misspeculating(); } 365 ThreadContext *tcBase() { return tc; } 366}; 367 368#endif // __CPU_SIMPLE_BASE_HH__ | 369#if FULL_SYSTEM 370 Fault hwrei() { return thread->hwrei(); } 371 void ev5_trap(Fault fault) { fault->invoke(tc); } 372 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 373#else 374 void syscall(int64_t callnum) { thread->syscall(callnum); } 375#endif 376 377 bool misspeculating() { return thread->misspeculating(); } 378 ThreadContext *tcBase() { return tc; } 379}; 380 381#endif // __CPU_SIMPLE_BASE_HH__ |