base.hh (4185:42c0395a03f9) base.hh (4240:cde9d7751cce)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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28 * Authors: Steve Reinhardt
29 * Dave Greene
30 * Nathan Binkert
31 */
32
33#ifndef __CPU_SIMPLE_BASE_HH__
34#define __CPU_SIMPLE_BASE_HH__
35
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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28 * Authors: Steve Reinhardt
29 * Dave Greene
30 * Nathan Binkert
31 */
32
33#ifndef __CPU_SIMPLE_BASE_HH__
34#define __CPU_SIMPLE_BASE_HH__
35
36#include "arch/predecoder.hh"
36#include "base/statistics.hh"
37#include "config/full_system.hh"
38#include "cpu/base.hh"
39#include "cpu/simple_thread.hh"
40#include "cpu/pc_event.hh"
41#include "cpu/static_inst.hh"
42#include "mem/packet.hh"
43#include "mem/port.hh"

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58
59class Process;
60
61#endif // FULL_SYSTEM
62
63class RemoteGDB;
64class GDBListener;
65
37#include "base/statistics.hh"
38#include "config/full_system.hh"
39#include "cpu/base.hh"
40#include "cpu/simple_thread.hh"
41#include "cpu/pc_event.hh"
42#include "cpu/static_inst.hh"
43#include "mem/packet.hh"
44#include "mem/port.hh"

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59
60class Process;
61
62#endif // FULL_SYSTEM
63
64class RemoteGDB;
65class GDBListener;
66
67namespace TheISA
68{
69 class Predecoder;
70}
66class ThreadContext;
67class Checkpoint;
68
69namespace Trace {
70 class InstRecord;
71}
72
73
74class BaseSimpleCPU : public BaseCPU
75{
76 protected:
71class ThreadContext;
72class Checkpoint;
73
74namespace Trace {
75 class InstRecord;
76}
77
78
79class BaseSimpleCPU : public BaseCPU
80{
81 protected:
77 typedef TheISA::MachInst MachInst;
78 typedef TheISA::MiscReg MiscReg;
79 typedef TheISA::FloatReg FloatReg;
80 typedef TheISA::FloatRegBits FloatRegBits;
81
82 protected:
83 Trace::InstRecord *traceData;
84
85 public:

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117
118#if FULL_SYSTEM
119 Addr dbg_vtophys(Addr addr);
120
121 bool interval_stats;
122#endif
123
124 // current instruction
82 typedef TheISA::MiscReg MiscReg;
83 typedef TheISA::FloatReg FloatReg;
84 typedef TheISA::FloatRegBits FloatRegBits;
85
86 protected:
87 Trace::InstRecord *traceData;
88
89 public:

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121
122#if FULL_SYSTEM
123 Addr dbg_vtophys(Addr addr);
124
125 bool interval_stats;
126#endif
127
128 // current instruction
125 MachInst inst;
129 TheISA::MachInst inst;
126
130
131 // The predecoder
132 TheISA::Predecoder predecoder;
133
127 // Static data storage
128 TheISA::LargestRead dataReg;
129
130 StaticInstPtr curStaticInst;
131 StaticInstPtr curMacroStaticInst;
132
133 void checkForInterrupts();
134 Fault setupFetchRequest(Request *req);

--- 218 unchanged lines hidden --- 		134 // Static data storage
135 TheISA::LargestRead dataReg;
136
137 StaticInstPtr curStaticInst;
138 StaticInstPtr curMacroStaticInst;
139
140 void checkForInterrupts();
141 Fault setupFetchRequest(Request *req);

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