base.hh (4182:5b2c0d266107) base.hh (4185:42c0395a03f9)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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28 * Authors: Steve Reinhardt
29 * Dave Greene
30 * Nathan Binkert
31 */
32
33#ifndef __CPU_SIMPLE_BASE_HH__
34#define __CPU_SIMPLE_BASE_HH__
35
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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28 * Authors: Steve Reinhardt
29 * Dave Greene
30 * Nathan Binkert
31 */
32
33#ifndef __CPU_SIMPLE_BASE_HH__
34#define __CPU_SIMPLE_BASE_HH__
35
36#include "arch/predecoder.hh"
37#include "base/statistics.hh"
38#include "config/full_system.hh"
39#include "cpu/base.hh"
40#include "cpu/simple_thread.hh"
41#include "cpu/pc_event.hh"
42#include "cpu/static_inst.hh"
43#include "mem/packet.hh"
44#include "mem/port.hh"

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59
60class Process;
61
62#endif // FULL_SYSTEM
63
64class RemoteGDB;
65class GDBListener;
66
36#include "base/statistics.hh"
37#include "config/full_system.hh"
38#include "cpu/base.hh"
39#include "cpu/simple_thread.hh"
40#include "cpu/pc_event.hh"
41#include "cpu/static_inst.hh"
42#include "mem/packet.hh"
43#include "mem/port.hh"

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58
59class Process;
60
61#endif // FULL_SYSTEM
62
63class RemoteGDB;
64class GDBListener;
65
67namespace TheISA
68{
69 class Predecoder;
70}
71class ThreadContext;
72class Checkpoint;
73
74namespace Trace {
75 class InstRecord;
76}
77
78
79class BaseSimpleCPU : public BaseCPU
80{
81 protected:
66class ThreadContext;
67class Checkpoint;
68
69namespace Trace {
70 class InstRecord;
71}
72
73
74class BaseSimpleCPU : public BaseCPU
75{
76 protected:
77 typedef TheISA::MachInst MachInst;
82 typedef TheISA::MiscReg MiscReg;
83 typedef TheISA::FloatReg FloatReg;
84 typedef TheISA::FloatRegBits FloatRegBits;
85
86 protected:
87 Trace::InstRecord *traceData;
88
89 public:

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121
122#if FULL_SYSTEM
123 Addr dbg_vtophys(Addr addr);
124
125 bool interval_stats;
126#endif
127
128 // current instruction
78 typedef TheISA::MiscReg MiscReg;
79 typedef TheISA::FloatReg FloatReg;
80 typedef TheISA::FloatRegBits FloatRegBits;
81
82 protected:
83 Trace::InstRecord *traceData;
84
85 public:

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117
118#if FULL_SYSTEM
119 Addr dbg_vtophys(Addr addr);
120
121 bool interval_stats;
122#endif
123
124 // current instruction
129 TheISA::MachInst inst;
125 MachInst inst;
130
126
131 // The predecoder
132 TheISA::Predecoder predecoder;
133
134 // Static data storage
135 TheISA::LargestRead dataReg;
136
137 StaticInstPtr curStaticInst;
138 StaticInstPtr curMacroStaticInst;
139
140 void checkForInterrupts();
141 Fault setupFetchRequest(Request *req);

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306 return thread->setMiscRegNoEffect(misc_reg, val);
307 }
308
309 void setMiscReg(int misc_reg, const MiscReg &val)
310 {
311 return thread->setMiscReg(misc_reg, val);
312 }
313
127 // Static data storage
128 TheISA::LargestRead dataReg;
129
130 StaticInstPtr curStaticInst;
131 StaticInstPtr curMacroStaticInst;
132
133 void checkForInterrupts();
134 Fault setupFetchRequest(Request *req);

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299 return thread->setMiscRegNoEffect(misc_reg, val);
300 }
301
302 void setMiscReg(int misc_reg, const MiscReg &val)
303 {
304 return thread->setMiscReg(misc_reg, val);
305 }
306
314 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
307 MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
315 {
316 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
317 return thread->readMiscRegNoEffect(reg_idx);
318 }
319
308 {
309 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
310 return thread->readMiscRegNoEffect(reg_idx);
311 }
312
320 MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx)
313 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
321 {
322 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
323 return thread->readMiscReg(reg_idx);
324 }
325
314 {
315 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
316 return thread->readMiscReg(reg_idx);
317 }
318
326 void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val)
319 void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val)
327 {
328 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
329 return thread->setMiscRegNoEffect(reg_idx, val);
330 }
331
320 {
321 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
322 return thread->setMiscRegNoEffect(reg_idx, val);
323 }
324
332 void setMiscRegOperandWithEffect(
325 void setMiscRegOperand(
333 const StaticInst *si, int idx, const MiscReg &val)
334 {
335 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
336 return thread->setMiscReg(reg_idx, val);
337 }
338
339 unsigned readStCondFailures() {
340 return thread->readStCondFailures();

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327 {
328 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
329 return thread->setMiscReg(reg_idx, val);
330 }
331
332 unsigned readStCondFailures() {
333 return thread->readStCondFailures();

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