base.hh (4181:6edaeff44647) base.hh (4182:5b2c0d266107)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 19 unchanged lines hidden (view full) ---

28 * Authors: Steve Reinhardt
29 * Dave Greene
30 * Nathan Binkert
31 */
32
33#ifndef __CPU_SIMPLE_BASE_HH__
34#define __CPU_SIMPLE_BASE_HH__
35
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 19 unchanged lines hidden (view full) ---

28 * Authors: Steve Reinhardt
29 * Dave Greene
30 * Nathan Binkert
31 */
32
33#ifndef __CPU_SIMPLE_BASE_HH__
34#define __CPU_SIMPLE_BASE_HH__
35
36#include "arch/predecoder.hh"
36#include "base/statistics.hh"
37#include "config/full_system.hh"
38#include "cpu/base.hh"
39#include "cpu/simple_thread.hh"
40#include "cpu/pc_event.hh"
41#include "cpu/static_inst.hh"
42#include "mem/packet.hh"
43#include "mem/port.hh"

--- 14 unchanged lines hidden (view full) ---

58
59class Process;
60
61#endif // FULL_SYSTEM
62
63class RemoteGDB;
64class GDBListener;
65
37#include "base/statistics.hh"
38#include "config/full_system.hh"
39#include "cpu/base.hh"
40#include "cpu/simple_thread.hh"
41#include "cpu/pc_event.hh"
42#include "cpu/static_inst.hh"
43#include "mem/packet.hh"
44#include "mem/port.hh"

--- 14 unchanged lines hidden (view full) ---

59
60class Process;
61
62#endif // FULL_SYSTEM
63
64class RemoteGDB;
65class GDBListener;
66
67namespace TheISA
68{
69 class Predecoder;
70}
66class ThreadContext;
67class Checkpoint;
68
69namespace Trace {
70 class InstRecord;
71}
72
73

--- 44 unchanged lines hidden (view full) ---

118 Addr dbg_vtophys(Addr addr);
119
120 bool interval_stats;
121#endif
122
123 // current instruction
124 TheISA::MachInst inst;
125
71class ThreadContext;
72class Checkpoint;
73
74namespace Trace {
75 class InstRecord;
76}
77
78

--- 44 unchanged lines hidden (view full) ---

123 Addr dbg_vtophys(Addr addr);
124
125 bool interval_stats;
126#endif
127
128 // current instruction
129 TheISA::MachInst inst;
130
126 // current extended machine instruction
127 TheISA::ExtMachInst extMachInst;
131 // The predecoder
132 TheISA::Predecoder predecoder;
128
129 // Static data storage
130 TheISA::LargestRead dataReg;
131
132 StaticInstPtr curStaticInst;
133 StaticInstPtr curMacroStaticInst;
134
135 void checkForInterrupts();

--- 219 unchanged lines hidden --- 		133
134 // Static data storage
135 TheISA::LargestRead dataReg;
136
137 StaticInstPtr curStaticInst;
138 StaticInstPtr curMacroStaticInst;
139
140 void checkForInterrupts();

--- 219 unchanged lines hidden ---