base.hh (4027:53292b42ee1c) | base.hh (4040:eb894f3fc168) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 111 unchanged lines hidden (view full) --- 120 121 bool interval_stats; 122#endif 123 124 // current instruction 125 MachInst inst; 126 127 // Static data storage | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 111 unchanged lines hidden (view full) --- 120 121 bool interval_stats; 122#endif 123 124 // current instruction 125 MachInst inst; 126 127 // Static data storage |
128 TheISA::IntReg dataReg; | 128 TheISA::LargestRead dataReg; |
129 130 StaticInstPtr curStaticInst; 131 StaticInstPtr curMacroStaticInst; 132 133 void checkForInterrupts(); 134 Fault setupFetchRequest(Request *req); 135 void preExecute(); 136 void postExecute(); --- 187 unchanged lines hidden (view full) --- 324 325 void setMiscRegOperandWithEffect( 326 const StaticInst *si, int idx, const MiscReg &val) 327 { 328 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 329 return thread->setMiscRegWithEffect(reg_idx, val); 330 } 331 | 129 130 StaticInstPtr curStaticInst; 131 StaticInstPtr curMacroStaticInst; 132 133 void checkForInterrupts(); 134 Fault setupFetchRequest(Request *req); 135 void preExecute(); 136 void postExecute(); --- 187 unchanged lines hidden (view full) --- 324 325 void setMiscRegOperandWithEffect( 326 const StaticInst *si, int idx, const MiscReg &val) 327 { 328 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 329 return thread->setMiscRegWithEffect(reg_idx, val); 330 } 331 |
332 unsigned readStCondFailures() { 333 return thread->readStCondFailures(); 334 } 335 336 void setStCondFailures(unsigned sc_failures) { 337 thread->setStCondFailures(sc_failures); 338 } 339 | |
340#if FULL_SYSTEM 341 Fault hwrei() { return thread->hwrei(); } 342 void ev5_trap(Fault fault) { fault->invoke(tc); } 343 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 344#else 345 void syscall(int64_t callnum) { thread->syscall(callnum); } 346#endif 347 348 bool misspeculating() { return thread->misspeculating(); } 349 ThreadContext *tcBase() { return tc; } 350}; 351 352#endif // __CPU_SIMPLE_BASE_HH__ | 332#if FULL_SYSTEM 333 Fault hwrei() { return thread->hwrei(); } 334 void ev5_trap(Fault fault) { fault->invoke(tc); } 335 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 336#else 337 void syscall(int64_t callnum) { thread->syscall(callnum); } 338#endif 339 340 bool misspeculating() { return thread->misspeculating(); } 341 ThreadContext *tcBase() { return tc; } 342}; 343 344#endif // __CPU_SIMPLE_BASE_HH__ |