base.hh (3792:dae368e56d0e) base.hh (3918:1f9a98d198e8)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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181 Counter lastDcacheRetry;
182
183 virtual void serialize(std::ostream &os);
184 virtual void unserialize(Checkpoint *cp, const std::string &section);
185
186 // These functions are only used in CPU models that split
187 // effective address computation from the actual memory access.
188 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 172 unchanged lines hidden (view full) ---

181 Counter lastDcacheRetry;
182
183 virtual void serialize(std::ostream &os);
184 virtual void unserialize(Checkpoint *cp, const std::string &section);
185
186 // These functions are only used in CPU models that split
187 // effective address computation from the actual memory access.
188 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
189 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); }
189 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n");
190 M5_DUMMY_RETURN}
190
191 void prefetch(Addr addr, unsigned flags)
192 {
193 // need to do this...
194 }
195
196 void writeHint(Addr addr, int size, unsigned flags)
197 {

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298 return thread->setMiscReg(misc_reg, val);
299 }
300
301 void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
302 {
303 return thread->setMiscRegWithEffect(misc_reg, val);
304 }
305
191
192 void prefetch(Addr addr, unsigned flags)
193 {
194 // need to do this...
195 }
196
197 void writeHint(Addr addr, int size, unsigned flags)
198 {

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299 return thread->setMiscReg(misc_reg, val);
300 }
301
302 void setMiscRegWithEffect(int misc_reg, const MiscReg &val)
303 {
304 return thread->setMiscRegWithEffect(misc_reg, val);
305 }
306
306 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
307 {
308 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
309 return thread->readMiscReg(reg_idx);
310 }
311
312 MiscReg readMiscRegOperandWithEffect(const StaticInst *si, int idx)
313 {
314 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
315 return thread->readMiscRegWithEffect(reg_idx);
316 }
317
318 void setMiscRegOperand(const StaticInst *si, int idx, const MiscReg &val)
319 {
320 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
321 return thread->setMiscReg(reg_idx, val);
322 }
323
324 void setMiscRegOperandWithEffect(
325 const StaticInst *si, int idx, const MiscReg &val)
326 {
327 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
328 return thread->setMiscRegWithEffect(reg_idx, val);
329 }
330
331#if FULL_SYSTEM
332 Fault hwrei() { return thread->hwrei(); }
333 void ev5_trap(Fault fault) { fault->invoke(tc); }
334 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
335#else
336 void syscall(int64_t callnum) { thread->syscall(callnum); }
337#endif
338
339 bool misspeculating() { return thread->misspeculating(); }
340 ThreadContext *tcBase() { return tc; }
341};
342
343#endif // __CPU_SIMPLE_BASE_HH__
307#if FULL_SYSTEM
308 Fault hwrei() { return thread->hwrei(); }
309 void ev5_trap(Fault fault) { fault->invoke(tc); }
310 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
311#else
312 void syscall(int64_t callnum) { thread->syscall(callnum); }
313#endif
314
315 bool misspeculating() { return thread->misspeculating(); }
316 ThreadContext *tcBase() { return tc; }
317};
318
319#endif // __CPU_SIMPLE_BASE_HH__