base.hh (3402:db60546818d0) base.hh (3453:c3ce58882751)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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42#include "mem/packet.hh"
43#include "mem/port.hh"
44#include "mem/request.hh"
45#include "sim/eventq.hh"
46
47// forward declarations
48#if FULL_SYSTEM
49class Processor;
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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42#include "mem/packet.hh"
43#include "mem/port.hh"
44#include "mem/request.hh"
45#include "sim/eventq.hh"
46
47// forward declarations
48#if FULL_SYSTEM
49class Processor;
50class AlphaITB;
51class AlphaDTB;
50namespace TheISA
51{
52 class ITB;
53 class DTB;
54}
52class MemObject;
53
54class RemoteGDB;
55class GDBListener;
56
57#else
58
59class Process;

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71class BaseSimpleCPU : public BaseCPU
72{
73 protected:
74 typedef TheISA::MachInst MachInst;
75 typedef TheISA::MiscReg MiscReg;
76 typedef TheISA::FloatReg FloatReg;
77 typedef TheISA::FloatRegBits FloatRegBits;
78
55class MemObject;
56
57class RemoteGDB;
58class GDBListener;
59
60#else
61
62class Process;

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74class BaseSimpleCPU : public BaseCPU
75{
76 protected:
77 typedef TheISA::MachInst MachInst;
78 typedef TheISA::MiscReg MiscReg;
79 typedef TheISA::FloatReg FloatReg;
80 typedef TheISA::FloatRegBits FloatRegBits;
81
82 MemObject *mem;
83
79 protected:
80 Trace::InstRecord *traceData;
81
82 public:
83 void post_interrupt(int int_num, int index);
84
85 void zero_fill_64(Addr addr) {
86 static int warned = 0;
87 if (!warned) {
88 warn ("WH64 is not implemented");
89 warned = 1;
90 }
91 };
92
93 public:
94 struct Params : public BaseCPU::Params
95 {
84 protected:
85 Trace::InstRecord *traceData;
86
87 public:
88 void post_interrupt(int int_num, int index);
89
90 void zero_fill_64(Addr addr) {
91 static int warned = 0;
92 if (!warned) {
93 warn ("WH64 is not implemented");
94 warned = 1;
95 }
96 };
97
98 public:
99 struct Params : public BaseCPU::Params
100 {
101 MemObject *mem;
96#if FULL_SYSTEM
102#if FULL_SYSTEM
97 AlphaITB *itb;
98 AlphaDTB *dtb;
103 TheISA::ITB *itb;
104 TheISA::DTB *dtb;
99#else
100 Process *process;
101#endif
102 };
103 BaseSimpleCPU(Params *params);
104 virtual ~BaseSimpleCPU();
105
106 public:

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106 Process *process;
107#endif
108 };
109 BaseSimpleCPU(Params *params);
110 virtual ~BaseSimpleCPU();
111
112 public:

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