base.hh (2680:246e7104f744) base.hh (2683:d6b72bb2ed97)
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 22 unchanged lines hidden (view full) ---

31 */
32
33#ifndef __CPU_SIMPLE_BASE_HH__
34#define __CPU_SIMPLE_BASE_HH__
35
36#include "base/statistics.hh"
37#include "config/full_system.hh"
38#include "cpu/base.hh"
1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 22 unchanged lines hidden (view full) ---

31 */
32
33#ifndef __CPU_SIMPLE_BASE_HH__
34#define __CPU_SIMPLE_BASE_HH__
35
36#include "base/statistics.hh"
37#include "config/full_system.hh"
38#include "cpu/base.hh"
39#include "cpu/cpu_exec_context.hh"
39#include "cpu/simple_thread.hh"
40#include "cpu/pc_event.hh"
41#include "cpu/sampler/sampler.hh"
42#include "cpu/static_inst.hh"
43#include "mem/packet.hh"
44#include "mem/port.hh"
45#include "mem/request.hh"
46#include "sim/eventq.hh"
47

--- 55 unchanged lines hidden (view full) ---

103#else
104 Process *process;
105#endif
106 };
107 BaseSimpleCPU(Params *params);
108 virtual ~BaseSimpleCPU();
109
110 public:
40#include "cpu/pc_event.hh"
41#include "cpu/sampler/sampler.hh"
42#include "cpu/static_inst.hh"
43#include "mem/packet.hh"
44#include "mem/port.hh"
45#include "mem/request.hh"
46#include "sim/eventq.hh"
47

--- 55 unchanged lines hidden (view full) ---

103#else
104 Process *process;
105#endif
106 };
107 BaseSimpleCPU(Params *params);
108 virtual ~BaseSimpleCPU();
109
110 public:
111 // execution context
112 CPUExecContext *cpuXC;
111 /** SimpleThread object, provides all the architectural state. */
112 SimpleThread *thread;
113
113
114 /** ThreadContext object, provides an interface for external
115 * objects to modify this thread's state.
116 */
114 ThreadContext *tc;
115
116#if FULL_SYSTEM
117 Addr dbg_vtophys(Addr addr);
118
119 bool interval_stats;
120#endif
121

--- 90 unchanged lines hidden (view full) ---

212 // raw pointer to the StaticInst is provided instead of a
213 // ref-counted StaticInstPtr to redice overhead. This is fine as
214 // long as these methods don't copy the pointer into any long-term
215 // storage (which is pretty hard to imagine they would have reason
216 // to do).
217
218 uint64_t readIntReg(const StaticInst *si, int idx)
219 {
117 ThreadContext *tc;
118
119#if FULL_SYSTEM
120 Addr dbg_vtophys(Addr addr);
121
122 bool interval_stats;
123#endif
124

--- 90 unchanged lines hidden (view full) ---

215 // raw pointer to the StaticInst is provided instead of a
216 // ref-counted StaticInstPtr to redice overhead. This is fine as
217 // long as these methods don't copy the pointer into any long-term
218 // storage (which is pretty hard to imagine they would have reason
219 // to do).
220
221 uint64_t readIntReg(const StaticInst *si, int idx)
222 {
220 return cpuXC->readIntReg(si->srcRegIdx(idx));
223 return thread->readIntReg(si->srcRegIdx(idx));
221 }
222
223 FloatReg readFloatReg(const StaticInst *si, int idx, int width)
224 {
225 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
224 }
225
226 FloatReg readFloatReg(const StaticInst *si, int idx, int width)
227 {
228 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
226 return cpuXC->readFloatReg(reg_idx, width);
229 return thread->readFloatReg(reg_idx, width);
227 }
228
229 FloatReg readFloatReg(const StaticInst *si, int idx)
230 {
231 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
230 }
231
232 FloatReg readFloatReg(const StaticInst *si, int idx)
233 {
234 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
232 return cpuXC->readFloatReg(reg_idx);
235 return thread->readFloatReg(reg_idx);
233 }
234
235 FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
236 {
237 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
236 }
237
238 FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
239 {
240 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
238 return cpuXC->readFloatRegBits(reg_idx, width);
241 return thread->readFloatRegBits(reg_idx, width);
239 }
240
241 FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
242 {
243 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
242 }
243
244 FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
245 {
246 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
244 return cpuXC->readFloatRegBits(reg_idx);
247 return thread->readFloatRegBits(reg_idx);
245 }
246
247 void setIntReg(const StaticInst *si, int idx, uint64_t val)
248 {
248 }
249
250 void setIntReg(const StaticInst *si, int idx, uint64_t val)
251 {
249 cpuXC->setIntReg(si->destRegIdx(idx), val);
252 thread->setIntReg(si->destRegIdx(idx), val);
250 }
251
252 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
253 {
254 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
253 }
254
255 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
256 {
257 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
255 cpuXC->setFloatReg(reg_idx, val, width);
258 thread->setFloatReg(reg_idx, val, width);
256 }
257
258 void setFloatReg(const StaticInst *si, int idx, FloatReg val)
259 {
260 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
259 }
260
261 void setFloatReg(const StaticInst *si, int idx, FloatReg val)
262 {
263 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
261 cpuXC->setFloatReg(reg_idx, val);
264 thread->setFloatReg(reg_idx, val);
262 }
263
264 void setFloatRegBits(const StaticInst *si, int idx,
265 FloatRegBits val, int width)
266 {
267 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
265 }
266
267 void setFloatRegBits(const StaticInst *si, int idx,
268 FloatRegBits val, int width)
269 {
270 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
268 cpuXC->setFloatRegBits(reg_idx, val, width);
271 thread->setFloatRegBits(reg_idx, val, width);
269 }
270
271 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
272 {
273 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
272 }
273
274 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
275 {
276 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
274 cpuXC->setFloatRegBits(reg_idx, val);
277 thread->setFloatRegBits(reg_idx, val);
275 }
276
278 }
279
277 uint64_t readPC() { return cpuXC->readPC(); }
278 uint64_t readNextPC() { return cpuXC->readNextPC(); }
279 uint64_t readNextNPC() { return cpuXC->readNextNPC(); }
280 uint64_t readPC() { return thread->readPC(); }
281 uint64_t readNextPC() { return thread->readNextPC(); }
282 uint64_t readNextNPC() { return thread->readNextNPC(); }
280
283
281 void setPC(uint64_t val) { cpuXC->setPC(val); }
282 void setNextPC(uint64_t val) { cpuXC->setNextPC(val); }
283 void setNextNPC(uint64_t val) { cpuXC->setNextNPC(val); }
284 void setPC(uint64_t val) { thread->setPC(val); }
285 void setNextPC(uint64_t val) { thread->setNextPC(val); }
286 void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
284
285 MiscReg readMiscReg(int misc_reg)
286 {
287
288 MiscReg readMiscReg(int misc_reg)
289 {
287 return cpuXC->readMiscReg(misc_reg);
290 return thread->readMiscReg(misc_reg);
288 }
289
290 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
291 {
291 }
292
293 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
294 {
292 return cpuXC->readMiscRegWithEffect(misc_reg, fault);
295 return thread->readMiscRegWithEffect(misc_reg, fault);
293 }
294
295 Fault setMiscReg(int misc_reg, const MiscReg &val)
296 {
296 }
297
298 Fault setMiscReg(int misc_reg, const MiscReg &val)
299 {
297 return cpuXC->setMiscReg(misc_reg, val);
300 return thread->setMiscReg(misc_reg, val);
298 }
299
300 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
301 {
301 }
302
303 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
304 {
302 return cpuXC->setMiscRegWithEffect(misc_reg, val);
305 return thread->setMiscRegWithEffect(misc_reg, val);
303 }
304
305#if FULL_SYSTEM
306 }
307
308#if FULL_SYSTEM
306 Fault hwrei() { return cpuXC->hwrei(); }
307 int readIntrFlag() { return cpuXC->readIntrFlag(); }
308 void setIntrFlag(int val) { cpuXC->setIntrFlag(val); }
309 bool inPalMode() { return cpuXC->inPalMode(); }
309 Fault hwrei() { return thread->hwrei(); }
310 int readIntrFlag() { return thread->readIntrFlag(); }
311 void setIntrFlag(int val) { thread->setIntrFlag(val); }
312 bool inPalMode() { return thread->inPalMode(); }
310 void ev5_trap(Fault fault) { fault->invoke(tc); }
313 void ev5_trap(Fault fault) { fault->invoke(tc); }
311 bool simPalCheck(int palFunc) { return cpuXC->simPalCheck(palFunc); }
314 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
312#else
315#else
313 void syscall(int64_t callnum) { cpuXC->syscall(callnum); }
316 void syscall(int64_t callnum) { thread->syscall(callnum); }
314#endif
315
317#endif
318
316 bool misspeculating() { return cpuXC->misspeculating(); }
319 bool misspeculating() { return thread->misspeculating(); }
317 ThreadContext *tcBase() { return tc; }
318};
319
320#endif // __CPU_SIMPLE_BASE_HH__
320 ThreadContext *tcBase() { return tc; }
321};
322
323#endif // __CPU_SIMPLE_BASE_HH__