base.hh (2665:a124942bacb8) | base.hh (2680:246e7104f744) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 47 unchanged lines hidden (view full) --- 56class GDBListener; 57 58#else 59 60class Process; 61 62#endif // FULL_SYSTEM 63 | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 47 unchanged lines hidden (view full) --- 56class GDBListener; 57 58#else 59 60class Process; 61 62#endif // FULL_SYSTEM 63 |
64class ExecContext; | 64class ThreadContext; |
65class Checkpoint; 66 67namespace Trace { 68 class InstRecord; 69} 70 71 72class BaseSimpleCPU : public BaseCPU --- 33 unchanged lines hidden (view full) --- 106 }; 107 BaseSimpleCPU(Params *params); 108 virtual ~BaseSimpleCPU(); 109 110 public: 111 // execution context 112 CPUExecContext *cpuXC; 113 | 65class Checkpoint; 66 67namespace Trace { 68 class InstRecord; 69} 70 71 72class BaseSimpleCPU : public BaseCPU --- 33 unchanged lines hidden (view full) --- 106 }; 107 BaseSimpleCPU(Params *params); 108 virtual ~BaseSimpleCPU(); 109 110 public: 111 // execution context 112 CPUExecContext *cpuXC; 113 |
114 ExecContext *xcProxy; | 114 ThreadContext *tc; |
115 116#if FULL_SYSTEM 117 Addr dbg_vtophys(Addr addr); 118 119 bool interval_stats; 120#endif 121 122 // current instruction --- 179 unchanged lines hidden (view full) --- 302 return cpuXC->setMiscRegWithEffect(misc_reg, val); 303 } 304 305#if FULL_SYSTEM 306 Fault hwrei() { return cpuXC->hwrei(); } 307 int readIntrFlag() { return cpuXC->readIntrFlag(); } 308 void setIntrFlag(int val) { cpuXC->setIntrFlag(val); } 309 bool inPalMode() { return cpuXC->inPalMode(); } | 115 116#if FULL_SYSTEM 117 Addr dbg_vtophys(Addr addr); 118 119 bool interval_stats; 120#endif 121 122 // current instruction --- 179 unchanged lines hidden (view full) --- 302 return cpuXC->setMiscRegWithEffect(misc_reg, val); 303 } 304 305#if FULL_SYSTEM 306 Fault hwrei() { return cpuXC->hwrei(); } 307 int readIntrFlag() { return cpuXC->readIntrFlag(); } 308 void setIntrFlag(int val) { cpuXC->setIntrFlag(val); } 309 bool inPalMode() { return cpuXC->inPalMode(); } |
310 void ev5_trap(Fault fault) { fault->invoke(xcProxy); } | 310 void ev5_trap(Fault fault) { fault->invoke(tc); } |
311 bool simPalCheck(int palFunc) { return cpuXC->simPalCheck(palFunc); } 312#else 313 void syscall(int64_t callnum) { cpuXC->syscall(callnum); } 314#endif 315 316 bool misspeculating() { return cpuXC->misspeculating(); } | 311 bool simPalCheck(int palFunc) { return cpuXC->simPalCheck(palFunc); } 312#else 313 void syscall(int64_t callnum) { cpuXC->syscall(callnum); } 314#endif 315 316 bool misspeculating() { return cpuXC->misspeculating(); } |
317 ExecContext *xcBase() { return xcProxy; } | 317 ThreadContext *tcBase() { return tc; } |
318}; 319 320#endif // __CPU_SIMPLE_BASE_HH__ | 318}; 319 320#endif // __CPU_SIMPLE_BASE_HH__ |