base.hh (11168:f98eb2da15a4) base.hh (11169:44b5c183c3cd)
1/*
2 * Copyright (c) 2011-2012,2015 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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89
90 void checkPcEventQueue();
91 void swapActiveThread();
92
93 public:
94 BaseSimpleCPU(BaseSimpleCPUParams *params);
95 virtual ~BaseSimpleCPU();
96 void wakeup(ThreadID tid) override;
1/*
2 * Copyright (c) 2011-2012,2015 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

--- 80 unchanged lines hidden (view full) ---

89
90 void checkPcEventQueue();
91 void swapActiveThread();
92
93 public:
94 BaseSimpleCPU(BaseSimpleCPUParams *params);
95 virtual ~BaseSimpleCPU();
96 void wakeup(ThreadID tid) override;
97 virtual void init();
97 void init() override;
98 public:
99 Trace::InstRecord *traceData;
100 CheckerCPU *checker;
101
102 std::vector<SimpleExecContext*> threadInfo;
103 std::list<ThreadID> activeThreads;
104
105 /** Current instruction */

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129
130
131 void checkForInterrupts();
132 void setupFetchRequest(Request *req);
133 void preExecute();
134 void postExecute();
135 void advancePC(const Fault &fault);
136
98 public:
99 Trace::InstRecord *traceData;
100 CheckerCPU *checker;
101
102 std::vector<SimpleExecContext*> threadInfo;
103 std::list<ThreadID> activeThreads;
104
105 /** Current instruction */

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129
130
131 void checkForInterrupts();
132 void setupFetchRequest(Request *req);
133 void preExecute();
134 void postExecute();
135 void advancePC(const Fault &fault);
136
137 virtual void haltContext(ThreadID thread_num);
137 void haltContext(ThreadID thread_num) override;
138
139 // statistics
138
139 // statistics
140 virtual void regStats();
141 virtual void resetStats();
140 void regStats() override;
141 void resetStats() override;
142
142
143 virtual void startup();
143 void startup() override;
144
145 virtual Fault readMem(Addr addr, uint8_t* data, unsigned size,
146 unsigned flags) = 0;
147
148 virtual Fault writeMem(uint8_t* data, unsigned size, Addr addr,
149 unsigned flags, uint64_t* res) = 0;
150
151 void countInst();
144
145 virtual Fault readMem(Addr addr, uint8_t* data, unsigned size,
146 unsigned flags) = 0;
147
148 virtual Fault writeMem(uint8_t* data, unsigned size, Addr addr,
149 unsigned flags, uint64_t* res) = 0;
150
151 void countInst();
152 virtual Counter totalInsts() const;
153 virtual Counter totalOps() const;
152 Counter totalInsts() const override;
153 Counter totalOps() const override;
154
155 void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
156 void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
157
158};
159
160#endif // __CPU_SIMPLE_BASE_HH__
154
155 void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
156 void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
157
158};
159
160#endif // __CPU_SIMPLE_BASE_HH__