base.hh (10934:5af8f40d8f2c) base.hh (10935:acd48ddd725f)
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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82
83class BaseSimpleCPU : public BaseCPU, public ExecContext
84{
85 protected:
86 typedef TheISA::MiscReg MiscReg;
87 typedef TheISA::FloatReg FloatReg;
88 typedef TheISA::FloatRegBits FloatRegBits;
89 typedef TheISA::CCReg CCReg;
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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82
83class BaseSimpleCPU : public BaseCPU, public ExecContext
84{
85 protected:
86 typedef TheISA::MiscReg MiscReg;
87 typedef TheISA::FloatReg FloatReg;
88 typedef TheISA::FloatRegBits FloatRegBits;
89 typedef TheISA::CCReg CCReg;
90 typedef TheISA::VectorReg VectorReg;
91
92 BPredUnit *branchPred;
93
94 protected:
95 Trace::InstRecord *traceData;
96
97 inline void checkPcEventQueue() {
98 Addr oldpc, pc = thread->instAddr();

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235 //number of float register file accesses
236 Stats::Scalar numFpRegReads;
237 Stats::Scalar numFpRegWrites;
238
239 //number of condition code register file accesses
240 Stats::Scalar numCCRegReads;
241 Stats::Scalar numCCRegWrites;
242
90
91 BPredUnit *branchPred;
92
93 protected:
94 Trace::InstRecord *traceData;
95
96 inline void checkPcEventQueue() {
97 Addr oldpc, pc = thread->instAddr();

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234 //number of float register file accesses
235 Stats::Scalar numFpRegReads;
236 Stats::Scalar numFpRegWrites;
237
238 //number of condition code register file accesses
239 Stats::Scalar numCCRegReads;
240 Stats::Scalar numCCRegWrites;
241
243 //number of vector register file accesses
244 Stats::Scalar numVectorRegReads;
245 Stats::Scalar numVectorRegWrites;
246
247 // number of simulated memory references
248 Stats::Scalar numMemRefs;
249 Stats::Scalar numLoadInsts;
250 Stats::Scalar numStoreInsts;
251
252 // number of idle cycles
253 Stats::Formula numIdleCycles;
254

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325
326 CCReg readCCRegOperand(const StaticInst *si, int idx)
327 {
328 numCCRegReads++;
329 int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
330 return thread->readCCReg(reg_idx);
331 }
332
242 // number of simulated memory references
243 Stats::Scalar numMemRefs;
244 Stats::Scalar numLoadInsts;
245 Stats::Scalar numStoreInsts;
246
247 // number of idle cycles
248 Stats::Formula numIdleCycles;
249

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320
321 CCReg readCCRegOperand(const StaticInst *si, int idx)
322 {
323 numCCRegReads++;
324 int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
325 return thread->readCCReg(reg_idx);
326 }
327
333 const VectorReg &readVectorRegOperand(const StaticInst *si, int idx)
334 {
335 numVectorRegReads++;
336 int reg_idx = si->srcRegIdx(idx) - TheISA::Vector_Reg_Base;
337 return thread->readVectorReg(reg_idx);
338 }
339
340 void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
341 {
342 numIntRegWrites++;
343 thread->setIntReg(si->destRegIdx(idx), val);
344 }
345
346 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
347 {

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360
361 void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
362 {
363 numCCRegWrites++;
364 int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
365 thread->setCCReg(reg_idx, val);
366 }
367
328 void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
329 {
330 numIntRegWrites++;
331 thread->setIntReg(si->destRegIdx(idx), val);
332 }
333
334 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
335 {

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348
349 void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
350 {
351 numCCRegWrites++;
352 int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
353 thread->setCCReg(reg_idx, val);
354 }
355
368 void setVectorRegOperand(const StaticInst *si, int idx,
369 const VectorReg &val)
370 {
371 numVectorRegWrites++;
372 int reg_idx = si->destRegIdx(idx) - TheISA::Vector_Reg_Base;
373 thread->setVectorReg(reg_idx, val);
374 }
375
376 bool readPredicate() { return thread->readPredicate(); }
377 void setPredicate(bool val)
378 {
379 thread->setPredicate(val);
380 if (traceData) {
381 traceData->setPredicate(val);
382 }
383 }

--- 103 unchanged lines hidden --- 		356 bool readPredicate() { return thread->readPredicate(); }
357 void setPredicate(bool val)
358 {
359 thread->setPredicate(val);
360 if (traceData) {
361 traceData->setPredicate(val);
362 }
363 }

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