base.hh (10193:d717abc806aa) base.hh (10319:4207f9bfcceb)
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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45
46#ifndef __CPU_SIMPLE_BASE_HH__
47#define __CPU_SIMPLE_BASE_HH__
48
49#include "base/statistics.hh"
50#include "config/the_isa.hh"
51#include "cpu/base.hh"
52#include "cpu/checker/cpu.hh"
1/*
2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
4 * All rights reserved
5 *
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating

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45
46#ifndef __CPU_SIMPLE_BASE_HH__
47#define __CPU_SIMPLE_BASE_HH__
48
49#include "base/statistics.hh"
50#include "config/the_isa.hh"
51#include "cpu/base.hh"
52#include "cpu/checker/cpu.hh"
53#include "cpu/exec_context.hh"
53#include "cpu/pc_event.hh"
54#include "cpu/simple_thread.hh"
55#include "cpu/static_inst.hh"
56#include "mem/packet.hh"
57#include "mem/port.hh"
58#include "mem/request.hh"
59#include "sim/eventq.hh"
60#include "sim/full_system.hh"

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74
75namespace Trace {
76 class InstRecord;
77}
78
79struct BaseSimpleCPUParams;
80class BPredUnit;
81
54#include "cpu/pc_event.hh"
55#include "cpu/simple_thread.hh"
56#include "cpu/static_inst.hh"
57#include "mem/packet.hh"
58#include "mem/port.hh"
59#include "mem/request.hh"
60#include "sim/eventq.hh"
61#include "sim/full_system.hh"

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75
76namespace Trace {
77 class InstRecord;
78}
79
80struct BaseSimpleCPUParams;
81class BPredUnit;
82
82class BaseSimpleCPU : public BaseCPU
83class BaseSimpleCPU : public BaseCPU, public ExecContext
83{
84 protected:
85 typedef TheISA::MiscReg MiscReg;
86 typedef TheISA::FloatReg FloatReg;
87 typedef TheISA::FloatRegBits FloatRegBits;
88 typedef TheISA::CCReg CCReg;
89
90 BPredUnit *branchPred;

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288
289 void serializeThread(std::ostream &os, ThreadID tid);
290 void unserializeThread(Checkpoint *cp, const std::string &section,
291 ThreadID tid);
292
293 // These functions are only used in CPU models that split
294 // effective address computation from the actual memory access.
295 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
84{
85 protected:
86 typedef TheISA::MiscReg MiscReg;
87 typedef TheISA::FloatReg FloatReg;
88 typedef TheISA::FloatRegBits FloatRegBits;
89 typedef TheISA::CCReg CCReg;
90
91 BPredUnit *branchPred;

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289
290 void serializeThread(std::ostream &os, ThreadID tid);
291 void unserializeThread(Checkpoint *cp, const std::string &section,
292 ThreadID tid);
293
294 // These functions are only used in CPU models that split
295 // effective address computation from the actual memory access.
296 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
296 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n");
297 M5_DUMMY_RETURN}
297 Addr getEA() const { panic("BaseSimpleCPU::getEA() not implemented\n"); }
298
299 // The register accessor methods provide the index of the
300 // instruction's operand (e.g., 0 or 1), not the architectural
301 // register index, to simplify the implementation of register
302 // renaming. We find the architectural register index by indexing
303 // into the instruction's own operand index table. Note that a
304 // raw pointer to the StaticInst is provided instead of a
305 // ref-counted StaticInstPtr to redice overhead. This is fine as
306 // long as these methods don't copy the pointer into any long-term
307 // storage (which is pretty hard to imagine they would have reason
308 // to do).
309
298
299 // The register accessor methods provide the index of the
300 // instruction's operand (e.g., 0 or 1), not the architectural
301 // register index, to simplify the implementation of register
302 // renaming. We find the architectural register index by indexing
303 // into the instruction's own operand index table. Note that a
304 // raw pointer to the StaticInst is provided instead of a
305 // ref-counted StaticInstPtr to redice overhead. This is fine as
306 // long as these methods don't copy the pointer into any long-term
307 // storage (which is pretty hard to imagine they would have reason
308 // to do).
309
310 uint64_t readIntRegOperand(const StaticInst *si, int idx)
310 IntReg readIntRegOperand(const StaticInst *si, int idx)
311 {
312 numIntRegReads++;
313 return thread->readIntReg(si->srcRegIdx(idx));
314 }
315
316 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
317 {
318 numFpRegReads++;

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329
330 CCReg readCCRegOperand(const StaticInst *si, int idx)
331 {
332 numCCRegReads++;
333 int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
334 return thread->readCCReg(reg_idx);
335 }
336
311 {
312 numIntRegReads++;
313 return thread->readIntReg(si->srcRegIdx(idx));
314 }
315
316 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
317 {
318 numFpRegReads++;

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329
330 CCReg readCCRegOperand(const StaticInst *si, int idx)
331 {
332 numCCRegReads++;
333 int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
334 return thread->readCCReg(reg_idx);
335 }
336
337 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
337 void setIntRegOperand(const StaticInst *si, int idx, IntReg val)
338 {
339 numIntRegWrites++;
340 thread->setIntReg(si->destRegIdx(idx), val);
341 }
342
343 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
344 {
345 numFpRegWrites++;

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365 bool readPredicate() { return thread->readPredicate(); }
366 void setPredicate(bool val)
367 {
368 thread->setPredicate(val);
369 if (traceData) {
370 traceData->setPredicate(val);
371 }
372 }
338 {
339 numIntRegWrites++;
340 thread->setIntReg(si->destRegIdx(idx), val);
341 }
342
343 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
344 {
345 numFpRegWrites++;

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365 bool readPredicate() { return thread->readPredicate(); }
366 void setPredicate(bool val)
367 {
368 thread->setPredicate(val);
369 if (traceData) {
370 traceData->setPredicate(val);
371 }
372 }
373 TheISA::PCState pcState() { return thread->pcState(); }
373 TheISA::PCState pcState() const { return thread->pcState(); }
374 void pcState(const TheISA::PCState &val) { thread->pcState(val); }
375 Addr instAddr() { return thread->instAddr(); }
376 Addr nextInstAddr() { return thread->nextInstAddr(); }
377 MicroPC microPC() { return thread->microPC(); }
378
379 MiscReg readMiscRegNoEffect(int misc_reg)
380 {
381 return thread->readMiscRegNoEffect(misc_reg);

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418 thread->demapInstPage(vaddr, asn);
419 }
420
421 void demapDataPage(Addr vaddr, uint64_t asn)
422 {
423 thread->demapDataPage(vaddr, asn);
424 }
425
374 void pcState(const TheISA::PCState &val) { thread->pcState(val); }
375 Addr instAddr() { return thread->instAddr(); }
376 Addr nextInstAddr() { return thread->nextInstAddr(); }
377 MicroPC microPC() { return thread->microPC(); }
378
379 MiscReg readMiscRegNoEffect(int misc_reg)
380 {
381 return thread->readMiscRegNoEffect(misc_reg);

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418 thread->demapInstPage(vaddr, asn);
419 }
420
421 void demapDataPage(Addr vaddr, uint64_t asn)
422 {
423 thread->demapDataPage(vaddr, asn);
424 }
425
426 unsigned readStCondFailures() {
426 unsigned int readStCondFailures() const {
427 return thread->readStCondFailures();
428 }
429
427 return thread->readStCondFailures();
428 }
429
430 void setStCondFailures(unsigned sc_failures) {
430 void setStCondFailures(unsigned int sc_failures) {
431 thread->setStCondFailures(sc_failures);
432 }
433
431 thread->setStCondFailures(sc_failures);
432 }
433
434 MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID)
435 {
434 MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID)
435 {
436 panic("Simple CPU models do not support multithreaded "
437 "register access.\n");
436 panic("Simple CPU models do not support multithreaded "
437 "register access.\n");
438 }
438 }
439
439
440 void setRegOtherThread(int regIdx, const MiscReg &val,
441 ThreadID tid = InvalidThreadID)
442 {
440 void setRegOtherThread(int regIdx, MiscReg val,
441 ThreadID tid = InvalidThreadID)
442 {
443 panic("Simple CPU models do not support multithreaded "
444 "register access.\n");
443 panic("Simple CPU models do not support multithreaded "
444 "register access.\n");
445 }
445 }
446
447 //Fault CacheOp(uint8_t Op, Addr EA);
448
449 Fault hwrei() { return thread->hwrei(); }
450 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
451
452 void
453 syscall(int64_t callnum)

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447 //Fault CacheOp(uint8_t Op, Addr EA);
448
449 Fault hwrei() { return thread->hwrei(); }
450 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
451
452 void
453 syscall(int64_t callnum)

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