1/* 2 * Copyright (c) 2011 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 34 unchanged lines hidden (view full) --- 43 */ 44 45#ifndef __CPU_SIMPLE_BASE_HH__ 46#define __CPU_SIMPLE_BASE_HH__ 47 48#include "arch/predecoder.hh" 49#include "base/statistics.hh" 50#include "config/the_isa.hh" |
51#include "cpu/base.hh" |
52#include "cpu/checker/cpu.hh" |
53#include "cpu/decode.hh" 54#include "cpu/pc_event.hh" 55#include "cpu/simple_thread.hh" 56#include "cpu/static_inst.hh" 57#include "mem/packet.hh" 58#include "mem/port.hh" 59#include "mem/request.hh" 60#include "sim/eventq.hh" 61#include "sim/full_system.hh" 62#include "sim/system.hh" 63 |
64// forward declarations 65class Checkpoint; 66class Process; 67class Processor; 68class ThreadContext; 69 70namespace TheISA 71{ --- 47 unchanged lines hidden (view full) --- 119 /** SimpleThread object, provides all the architectural state. */ 120 SimpleThread *thread; 121 122 /** ThreadContext object, provides an interface for external 123 * objects to modify this thread's state. 124 */ 125 ThreadContext *tc; 126 |
127 CheckerCPU *checker; |
128 |
129 protected: 130 131 enum Status { 132 Idle, 133 Running, 134 Faulting, 135 ITBWaitResponse, 136 IcacheRetry, --- 299 unchanged lines hidden --- |