1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 30 unchanged lines hidden (view full) --- 39#include "cpu/base.hh" 40#include "cpu/simple_thread.hh" 41#include "cpu/pc_event.hh" 42#include "cpu/static_inst.hh" 43#include "mem/packet.hh" 44#include "mem/port.hh" 45#include "mem/request.hh" 46#include "sim/eventq.hh" |
47#include "sim/system.hh" |
48 49// forward declarations 50#if FULL_SYSTEM 51class Processor; 52namespace TheISA 53{ 54 class ITB; 55 class DTB; --- 26 unchanged lines hidden (view full) --- 82 protected: 83 typedef TheISA::MiscReg MiscReg; 84 typedef TheISA::FloatReg FloatReg; 85 typedef TheISA::FloatRegBits FloatRegBits; 86 87 protected: 88 Trace::InstRecord *traceData; 89 |
90 inline void checkPcEventQueue() { 91 Addr oldpc; 92 do { 93 oldpc = thread->readPC(); 94 system->pcEventQueue.service(tc); 95 } while (oldpc != thread->readPC()); 96 } 97 |
98 public: 99 void post_interrupt(int int_num, int index); 100 101 void zero_fill_64(Addr addr) { 102 static int warned = 0; 103 if (!warned) { 104 warn ("WH64 is not implemented"); 105 warned = 1; --- 299 unchanged lines hidden --- |