1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 62 unchanged lines hidden (view full) --- 71class BaseSimpleCPU : public BaseCPU 72{ 73 protected: 74 typedef TheISA::MachInst MachInst; 75 typedef TheISA::MiscReg MiscReg; 76 typedef TheISA::FloatReg FloatReg; 77 typedef TheISA::FloatRegBits FloatRegBits; 78 |
79 protected: 80 Trace::InstRecord *traceData; 81 82 public: 83 void post_interrupt(int int_num, int index); 84 85 void zero_fill_64(Addr addr) { 86 static int warned = 0; 87 if (!warned) { 88 warn ("WH64 is not implemented"); 89 warned = 1; 90 } 91 }; 92 93 public: 94 struct Params : public BaseCPU::Params 95 { |
96#if FULL_SYSTEM 97 AlphaITB *itb; 98 AlphaDTB *dtb; 99#else 100 Process *process; 101#endif 102 }; 103 BaseSimpleCPU(Params *params); --- 212 unchanged lines hidden --- |