1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 24 unchanged lines hidden (view full) --- 33#ifndef __CPU_SIMPLE_BASE_HH__ 34#define __CPU_SIMPLE_BASE_HH__ 35 36#include "base/statistics.hh" 37#include "config/full_system.hh" 38#include "cpu/base.hh" 39#include "cpu/simple_thread.hh" 40#include "cpu/pc_event.hh" |
41#include "cpu/static_inst.hh" 42#include "mem/packet.hh" 43#include "mem/port.hh" 44#include "mem/request.hh" 45#include "sim/eventq.hh" 46 47// forward declarations 48#if FULL_SYSTEM --- 73 unchanged lines hidden (view full) --- 122#endif 123 124 // current instruction 125 MachInst inst; 126 127 // Static data storage 128 TheISA::IntReg dataReg; 129 |
130 StaticInstPtr curStaticInst; 131 132 void checkForInterrupts(); 133 Fault setupFetchRequest(Request *req); 134 void preExecute(); 135 void postExecute(); 136 void advancePC(Fault fault); 137 --- 180 unchanged lines hidden --- |