1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Dave Greene 30 * Nathan Binkert 31 */ 32 33#ifndef __CPU_SIMPLE_BASE_HH__ 34#define __CPU_SIMPLE_BASE_HH__ 35 36#include "arch/predecoder.hh" 37#include "base/statistics.hh" 38#include "config/full_system.hh" 39#include "config/the_isa.hh" 40#include "cpu/base.hh" 41#include "cpu/simple_thread.hh" 42#include "cpu/pc_event.hh" 43#include "cpu/static_inst.hh" 44#include "mem/packet.hh" 45#include "mem/port.hh" 46#include "mem/request.hh" 47#include "sim/eventq.hh" 48#include "sim/system.hh" 49 50// forward declarations 51#if FULL_SYSTEM 52class Processor; 53namespace TheISA 54{ 55 class ITB; 56 class DTB; 57} 58class MemObject; 59 60#else 61 62class Process; 63 64#endif // FULL_SYSTEM 65 66namespace TheISA 67{ 68 class Predecoder; 69} 70class ThreadContext; 71class Checkpoint; 72 73namespace Trace { 74 class InstRecord; 75} 76 77class BaseSimpleCPUParams; 78 79 80class BaseSimpleCPU : public BaseCPU 81{ 82 protected: 83 typedef TheISA::MiscReg MiscReg; 84 typedef TheISA::FloatReg FloatReg; 85 typedef TheISA::FloatRegBits FloatRegBits; 86 87 protected: 88 Trace::InstRecord *traceData; 89 90 inline void checkPcEventQueue() { 91 Addr oldpc, pc = thread->instAddr(); 92 do { 93 oldpc = pc; 94 system->pcEventQueue.service(tc); 95 pc = thread->instAddr(); 96 } while (oldpc != pc); 97 } 98 99 public: 100 void wakeup(); 101 102 void zero_fill_64(Addr addr) { 103 static int warned = 0; 104 if (!warned) { 105 warn ("WH64 is not implemented"); 106 warned = 1; 107 } 108 }; 109 110 public: 111 BaseSimpleCPU(BaseSimpleCPUParams *params); 112 virtual ~BaseSimpleCPU(); 113 114 public: 115 /** SimpleThread object, provides all the architectural state. */ 116 SimpleThread *thread; 117 118 /** ThreadContext object, provides an interface for external 119 * objects to modify this thread's state. 120 */ 121 ThreadContext *tc; 122 protected: 123 124 enum Status { 125 Idle, 126 Running, 127 ITBWaitResponse, 128 IcacheRetry, 129 IcacheWaitResponse, 130 IcacheWaitSwitch, 131 DTBWaitResponse, 132 DcacheRetry, 133 DcacheWaitResponse, 134 DcacheWaitSwitch, 135 SwitchedOut 136 }; 137 138 Status _status; 139 140 public: 141 142#if FULL_SYSTEM 143 Addr dbg_vtophys(Addr addr); 144 145 bool interval_stats; 146#endif 147 148 // current instruction 149 TheISA::MachInst inst; 150 151 // The predecoder 152 TheISA::Predecoder predecoder; 153 154 StaticInstPtr curStaticInst; 155 StaticInstPtr curMacroStaticInst; 156 157 //This is the offset from the current pc that fetch should be performed at 158 Addr fetchOffset; 159 //This flag says to stay at the current pc. This is useful for 160 //instructions which go beyond MachInst boundaries. 161 bool stayAtPC; 162 163 void checkForInterrupts(); 164 void setupFetchRequest(Request *req); 165 void preExecute(); 166 void postExecute(); 167 void advancePC(Fault fault); 168 169 virtual void deallocateContext(int thread_num); 170 virtual void haltContext(int thread_num); 171 172 // statistics 173 virtual void regStats(); 174 virtual void resetStats(); 175 176 // number of simulated instructions 177 Counter numInst; 178 Counter startNumInst; 179 Stats::Scalar numInsts; 180 181 void countInst() 182 { 183 numInst++; 184 numInsts++;
| 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Steve Reinhardt 29 * Dave Greene 30 * Nathan Binkert 31 */ 32 33#ifndef __CPU_SIMPLE_BASE_HH__ 34#define __CPU_SIMPLE_BASE_HH__ 35 36#include "arch/predecoder.hh" 37#include "base/statistics.hh" 38#include "config/full_system.hh" 39#include "config/the_isa.hh" 40#include "cpu/base.hh" 41#include "cpu/simple_thread.hh" 42#include "cpu/pc_event.hh" 43#include "cpu/static_inst.hh" 44#include "mem/packet.hh" 45#include "mem/port.hh" 46#include "mem/request.hh" 47#include "sim/eventq.hh" 48#include "sim/system.hh" 49 50// forward declarations 51#if FULL_SYSTEM 52class Processor; 53namespace TheISA 54{ 55 class ITB; 56 class DTB; 57} 58class MemObject; 59 60#else 61 62class Process; 63 64#endif // FULL_SYSTEM 65 66namespace TheISA 67{ 68 class Predecoder; 69} 70class ThreadContext; 71class Checkpoint; 72 73namespace Trace { 74 class InstRecord; 75} 76 77class BaseSimpleCPUParams; 78 79 80class BaseSimpleCPU : public BaseCPU 81{ 82 protected: 83 typedef TheISA::MiscReg MiscReg; 84 typedef TheISA::FloatReg FloatReg; 85 typedef TheISA::FloatRegBits FloatRegBits; 86 87 protected: 88 Trace::InstRecord *traceData; 89 90 inline void checkPcEventQueue() { 91 Addr oldpc, pc = thread->instAddr(); 92 do { 93 oldpc = pc; 94 system->pcEventQueue.service(tc); 95 pc = thread->instAddr(); 96 } while (oldpc != pc); 97 } 98 99 public: 100 void wakeup(); 101 102 void zero_fill_64(Addr addr) { 103 static int warned = 0; 104 if (!warned) { 105 warn ("WH64 is not implemented"); 106 warned = 1; 107 } 108 }; 109 110 public: 111 BaseSimpleCPU(BaseSimpleCPUParams *params); 112 virtual ~BaseSimpleCPU(); 113 114 public: 115 /** SimpleThread object, provides all the architectural state. */ 116 SimpleThread *thread; 117 118 /** ThreadContext object, provides an interface for external 119 * objects to modify this thread's state. 120 */ 121 ThreadContext *tc; 122 protected: 123 124 enum Status { 125 Idle, 126 Running, 127 ITBWaitResponse, 128 IcacheRetry, 129 IcacheWaitResponse, 130 IcacheWaitSwitch, 131 DTBWaitResponse, 132 DcacheRetry, 133 DcacheWaitResponse, 134 DcacheWaitSwitch, 135 SwitchedOut 136 }; 137 138 Status _status; 139 140 public: 141 142#if FULL_SYSTEM 143 Addr dbg_vtophys(Addr addr); 144 145 bool interval_stats; 146#endif 147 148 // current instruction 149 TheISA::MachInst inst; 150 151 // The predecoder 152 TheISA::Predecoder predecoder; 153 154 StaticInstPtr curStaticInst; 155 StaticInstPtr curMacroStaticInst; 156 157 //This is the offset from the current pc that fetch should be performed at 158 Addr fetchOffset; 159 //This flag says to stay at the current pc. This is useful for 160 //instructions which go beyond MachInst boundaries. 161 bool stayAtPC; 162 163 void checkForInterrupts(); 164 void setupFetchRequest(Request *req); 165 void preExecute(); 166 void postExecute(); 167 void advancePC(Fault fault); 168 169 virtual void deallocateContext(int thread_num); 170 virtual void haltContext(int thread_num); 171 172 // statistics 173 virtual void regStats(); 174 virtual void resetStats(); 175 176 // number of simulated instructions 177 Counter numInst; 178 Counter startNumInst; 179 Stats::Scalar numInsts; 180 181 void countInst() 182 { 183 numInst++; 184 numInsts++;
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185
| 185 system->totalNumInsts++;
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186 thread->funcExeInst++; 187 } 188 189 virtual Counter totalInstructions() const 190 { 191 return numInst - startNumInst; 192 } 193
| 186 thread->funcExeInst++; 187 } 188 189 virtual Counter totalInstructions() const 190 { 191 return numInst - startNumInst; 192 } 193
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| 194 //number of integer alu accesses 195 Stats::Scalar numIntAluAccesses; 196 197 //number of float alu accesses 198 Stats::Scalar numFpAluAccesses; 199 200 //number of function calls/returns 201 Stats::Scalar numCallsReturns; 202 203 //conditional control instructions; 204 Stats::Scalar numCondCtrlInsts; 205 206 //number of int instructions 207 Stats::Scalar numIntInsts; 208 209 //number of float instructions 210 Stats::Scalar numFpInsts; 211 212 //number of integer register file accesses 213 Stats::Scalar numIntRegReads; 214 Stats::Scalar numIntRegWrites; 215 216 //number of float register file accesses 217 Stats::Scalar numFpRegReads; 218 Stats::Scalar numFpRegWrites; 219
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194 // number of simulated memory references 195 Stats::Scalar numMemRefs;
| 220 // number of simulated memory references 221 Stats::Scalar numMemRefs;
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| 222 Stats::Scalar numLoadInsts; 223 Stats::Scalar numStoreInsts;
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196
| 224
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| 225 // number of idle cycles 226 Stats::Formula numIdleCycles; 227 228 // number of busy cycles 229 Stats::Formula numBusyCycles; 230
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197 // number of simulated loads 198 Counter numLoad; 199 Counter startNumLoad; 200 201 // number of idle cycles 202 Stats::Average notIdleFraction; 203 Stats::Formula idleFraction; 204 205 // number of cycles stalled for I-cache responses 206 Stats::Scalar icacheStallCycles; 207 Counter lastIcacheStall; 208 209 // number of cycles stalled for I-cache retries 210 Stats::Scalar icacheRetryCycles; 211 Counter lastIcacheRetry; 212 213 // number of cycles stalled for D-cache responses 214 Stats::Scalar dcacheStallCycles; 215 Counter lastDcacheStall; 216 217 // number of cycles stalled for D-cache retries 218 Stats::Scalar dcacheRetryCycles; 219 Counter lastDcacheRetry; 220 221 virtual void serialize(std::ostream &os); 222 virtual void unserialize(Checkpoint *cp, const std::string §ion); 223 224 // These functions are only used in CPU models that split 225 // effective address computation from the actual memory access. 226 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); } 227 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); 228 M5_DUMMY_RETURN} 229 230 // The register accessor methods provide the index of the 231 // instruction's operand (e.g., 0 or 1), not the architectural 232 // register index, to simplify the implementation of register 233 // renaming. We find the architectural register index by indexing 234 // into the instruction's own operand index table. Note that a 235 // raw pointer to the StaticInst is provided instead of a 236 // ref-counted StaticInstPtr to redice overhead. This is fine as 237 // long as these methods don't copy the pointer into any long-term 238 // storage (which is pretty hard to imagine they would have reason 239 // to do). 240 241 uint64_t readIntRegOperand(const StaticInst *si, int idx) 242 {
| 231 // number of simulated loads 232 Counter numLoad; 233 Counter startNumLoad; 234 235 // number of idle cycles 236 Stats::Average notIdleFraction; 237 Stats::Formula idleFraction; 238 239 // number of cycles stalled for I-cache responses 240 Stats::Scalar icacheStallCycles; 241 Counter lastIcacheStall; 242 243 // number of cycles stalled for I-cache retries 244 Stats::Scalar icacheRetryCycles; 245 Counter lastIcacheRetry; 246 247 // number of cycles stalled for D-cache responses 248 Stats::Scalar dcacheStallCycles; 249 Counter lastDcacheStall; 250 251 // number of cycles stalled for D-cache retries 252 Stats::Scalar dcacheRetryCycles; 253 Counter lastDcacheRetry; 254 255 virtual void serialize(std::ostream &os); 256 virtual void unserialize(Checkpoint *cp, const std::string §ion); 257 258 // These functions are only used in CPU models that split 259 // effective address computation from the actual memory access. 260 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); } 261 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); 262 M5_DUMMY_RETURN} 263 264 // The register accessor methods provide the index of the 265 // instruction's operand (e.g., 0 or 1), not the architectural 266 // register index, to simplify the implementation of register 267 // renaming. We find the architectural register index by indexing 268 // into the instruction's own operand index table. Note that a 269 // raw pointer to the StaticInst is provided instead of a 270 // ref-counted StaticInstPtr to redice overhead. This is fine as 271 // long as these methods don't copy the pointer into any long-term 272 // storage (which is pretty hard to imagine they would have reason 273 // to do). 274 275 uint64_t readIntRegOperand(const StaticInst *si, int idx) 276 {
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| 277 numIntRegReads++;
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243 return thread->readIntReg(si->srcRegIdx(idx)); 244 } 245 246 FloatReg readFloatRegOperand(const StaticInst *si, int idx) 247 {
| 278 return thread->readIntReg(si->srcRegIdx(idx)); 279 } 280 281 FloatReg readFloatRegOperand(const StaticInst *si, int idx) 282 {
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| 283 numFpRegReads++;
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248 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 249 return thread->readFloatReg(reg_idx); 250 } 251 252 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 253 {
| 284 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 285 return thread->readFloatReg(reg_idx); 286 } 287 288 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) 289 {
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| 290 numFpRegReads++;
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254 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 255 return thread->readFloatRegBits(reg_idx); 256 } 257 258 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 259 {
| 291 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag; 292 return thread->readFloatRegBits(reg_idx); 293 } 294 295 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val) 296 {
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| 297 numIntRegWrites++;
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260 thread->setIntReg(si->destRegIdx(idx), val); 261 } 262 263 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 264 {
| 298 thread->setIntReg(si->destRegIdx(idx), val); 299 } 300 301 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val) 302 {
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| 303 numFpRegWrites++;
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265 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 266 thread->setFloatReg(reg_idx, val); 267 } 268 269 void setFloatRegOperandBits(const StaticInst *si, int idx, 270 FloatRegBits val) 271 {
| 304 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 305 thread->setFloatReg(reg_idx, val); 306 } 307 308 void setFloatRegOperandBits(const StaticInst *si, int idx, 309 FloatRegBits val) 310 {
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| 311 numFpRegWrites++;
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272 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 273 thread->setFloatRegBits(reg_idx, val); 274 } 275 276 bool readPredicate() { return thread->readPredicate(); } 277 void setPredicate(bool val) 278 { 279 thread->setPredicate(val); 280 if (traceData) { 281 traceData->setPredicate(val); 282 } 283 } 284 TheISA::PCState pcState() { return thread->pcState(); } 285 void pcState(const TheISA::PCState &val) { thread->pcState(val); } 286 Addr instAddr() { return thread->instAddr(); } 287 Addr nextInstAddr() { return thread->nextInstAddr(); } 288 MicroPC microPC() { return thread->microPC(); } 289 290 MiscReg readMiscRegNoEffect(int misc_reg) 291 { 292 return thread->readMiscRegNoEffect(misc_reg); 293 } 294 295 MiscReg readMiscReg(int misc_reg) 296 {
| 312 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag; 313 thread->setFloatRegBits(reg_idx, val); 314 } 315 316 bool readPredicate() { return thread->readPredicate(); } 317 void setPredicate(bool val) 318 { 319 thread->setPredicate(val); 320 if (traceData) { 321 traceData->setPredicate(val); 322 } 323 } 324 TheISA::PCState pcState() { return thread->pcState(); } 325 void pcState(const TheISA::PCState &val) { thread->pcState(val); } 326 Addr instAddr() { return thread->instAddr(); } 327 Addr nextInstAddr() { return thread->nextInstAddr(); } 328 MicroPC microPC() { return thread->microPC(); } 329 330 MiscReg readMiscRegNoEffect(int misc_reg) 331 { 332 return thread->readMiscRegNoEffect(misc_reg); 333 } 334 335 MiscReg readMiscReg(int misc_reg) 336 {
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| 337 numIntRegReads++;
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297 return thread->readMiscReg(misc_reg); 298 } 299 300 void setMiscReg(int misc_reg, const MiscReg &val) 301 {
| 338 return thread->readMiscReg(misc_reg); 339 } 340 341 void setMiscReg(int misc_reg, const MiscReg &val) 342 {
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| 343 numIntRegWrites++;
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302 return thread->setMiscReg(misc_reg, val); 303 } 304 305 MiscReg readMiscRegOperand(const StaticInst *si, int idx) 306 {
| 344 return thread->setMiscReg(misc_reg, val); 345 } 346 347 MiscReg readMiscRegOperand(const StaticInst *si, int idx) 348 {
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| 349 numIntRegReads++;
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307 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 308 return thread->readMiscReg(reg_idx); 309 } 310 311 void setMiscRegOperand( 312 const StaticInst *si, int idx, const MiscReg &val) 313 {
| 350 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 351 return thread->readMiscReg(reg_idx); 352 } 353 354 void setMiscRegOperand( 355 const StaticInst *si, int idx, const MiscReg &val) 356 {
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| 357 numIntRegWrites++;
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314 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 315 return thread->setMiscReg(reg_idx, val); 316 } 317 318 void demapPage(Addr vaddr, uint64_t asn) 319 { 320 thread->demapPage(vaddr, asn); 321 } 322 323 void demapInstPage(Addr vaddr, uint64_t asn) 324 { 325 thread->demapInstPage(vaddr, asn); 326 } 327 328 void demapDataPage(Addr vaddr, uint64_t asn) 329 { 330 thread->demapDataPage(vaddr, asn); 331 } 332 333 unsigned readStCondFailures() { 334 return thread->readStCondFailures(); 335 } 336 337 void setStCondFailures(unsigned sc_failures) { 338 thread->setStCondFailures(sc_failures); 339 } 340 341 MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID) 342 { 343 panic("Simple CPU models do not support multithreaded " 344 "register access.\n"); 345 } 346 347 void setRegOtherThread(int regIdx, const MiscReg &val, 348 ThreadID tid = InvalidThreadID) 349 { 350 panic("Simple CPU models do not support multithreaded " 351 "register access.\n"); 352 } 353 354 //Fault CacheOp(uint8_t Op, Addr EA); 355 356#if FULL_SYSTEM 357 Fault hwrei() { return thread->hwrei(); } 358 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 359#else 360 void syscall(int64_t callnum) { thread->syscall(callnum); } 361#endif 362 363 bool misspeculating() { return thread->misspeculating(); } 364 ThreadContext *tcBase() { return tc; } 365}; 366 367#endif // __CPU_SIMPLE_BASE_HH__
| 358 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag; 359 return thread->setMiscReg(reg_idx, val); 360 } 361 362 void demapPage(Addr vaddr, uint64_t asn) 363 { 364 thread->demapPage(vaddr, asn); 365 } 366 367 void demapInstPage(Addr vaddr, uint64_t asn) 368 { 369 thread->demapInstPage(vaddr, asn); 370 } 371 372 void demapDataPage(Addr vaddr, uint64_t asn) 373 { 374 thread->demapDataPage(vaddr, asn); 375 } 376 377 unsigned readStCondFailures() { 378 return thread->readStCondFailures(); 379 } 380 381 void setStCondFailures(unsigned sc_failures) { 382 thread->setStCondFailures(sc_failures); 383 } 384 385 MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID) 386 { 387 panic("Simple CPU models do not support multithreaded " 388 "register access.\n"); 389 } 390 391 void setRegOtherThread(int regIdx, const MiscReg &val, 392 ThreadID tid = InvalidThreadID) 393 { 394 panic("Simple CPU models do not support multithreaded " 395 "register access.\n"); 396 } 397 398 //Fault CacheOp(uint8_t Op, Addr EA); 399 400#if FULL_SYSTEM 401 Fault hwrei() { return thread->hwrei(); } 402 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); } 403#else 404 void syscall(int64_t callnum) { thread->syscall(callnum); } 405#endif 406 407 bool misspeculating() { return thread->misspeculating(); } 408 ThreadContext *tcBase() { return tc; } 409}; 410 411#endif // __CPU_SIMPLE_BASE_HH__
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