1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Dave Greene
30 * Nathan Binkert
31 */
32
33#ifndef __CPU_SIMPLE_BASE_HH__
34#define __CPU_SIMPLE_BASE_HH__
35
36#include "arch/predecoder.hh"
37#include "base/statistics.hh"
38#include "config/full_system.hh"
39#include "cpu/base.hh"
40#include "cpu/simple_thread.hh"
41#include "cpu/pc_event.hh"
42#include "cpu/static_inst.hh"
43#include "mem/packet.hh"
44#include "mem/port.hh"
45#include "mem/request.hh"
46#include "sim/eventq.hh"
47#include "sim/system.hh"
48
49// forward declarations
50#if FULL_SYSTEM
51class Processor;
52namespace TheISA
53{
54 class ITB;
55 class DTB;
56}
57class MemObject;
58
59#else
60
61class Process;
62
63#endif // FULL_SYSTEM
64
65class RemoteGDB;
66class GDBListener;
67
68namespace TheISA
69{
70 class Predecoder;
71}
72class ThreadContext;
73class Checkpoint;
74
75namespace Trace {
76 class InstRecord;
77}
78
79class BaseSimpleCPUParams;
80
81
82class BaseSimpleCPU : public BaseCPU
83{
84 protected:
85 typedef TheISA::MiscReg MiscReg;
86 typedef TheISA::FloatReg FloatReg;
87 typedef TheISA::FloatRegBits FloatRegBits;
88
89 protected:
90 Trace::InstRecord *traceData;
91
92 inline void checkPcEventQueue() {
93 Addr oldpc;
94 do {
95 oldpc = thread->readPC();
96 system->pcEventQueue.service(tc);
97 } while (oldpc != thread->readPC());
98 }
99
100 public:
101 void post_interrupt(int int_num, int index);
102
103 void zero_fill_64(Addr addr) {
104 static int warned = 0;
105 if (!warned) {
106 warn ("WH64 is not implemented");
107 warned = 1;
108 }
109 };
110
111 public:
112 BaseSimpleCPU(BaseSimpleCPUParams *params);
113 virtual ~BaseSimpleCPU();
114
115 public:
116 /** SimpleThread object, provides all the architectural state. */
117 SimpleThread *thread;
118
119 /** ThreadContext object, provides an interface for external
120 * objects to modify this thread's state.
121 */
122 ThreadContext *tc;
123 protected:
124 int cpuId;
125
126 enum Status {
127 Idle,
128 Running,
129 IcacheRetry,
130 IcacheWaitResponse,
131 IcacheWaitSwitch,
132 DcacheRetry,
133 DcacheWaitResponse,
134 DcacheWaitSwitch,
135 SwitchedOut
136 };
137
138 Status _status;
139
140 public:
141
142#if FULL_SYSTEM
143 Addr dbg_vtophys(Addr addr);
144
145 bool interval_stats;
146#endif
147
148 // current instruction
149 TheISA::MachInst inst;
150
151 // The predecoder
152 TheISA::Predecoder predecoder;
153
154 StaticInstPtr curStaticInst;
155 StaticInstPtr curMacroStaticInst;
156
157 //This is the offset from the current pc that fetch should be performed at
158 Addr fetchOffset;
159 //This flag says to stay at the current pc. This is useful for
160 //instructions which go beyond MachInst boundaries.
161 bool stayAtPC;
162
163 void checkForInterrupts();
164 Fault setupFetchRequest(Request *req);
165 void preExecute();
166 void postExecute();
167 void advancePC(Fault fault);
168
169 virtual void deallocateContext(int thread_num);
170 virtual void haltContext(int thread_num);
171
172 // statistics
173 virtual void regStats();
174 virtual void resetStats();
175
176 // number of simulated instructions
177 Counter numInst;
178 Counter startNumInst;
179 Stats::Scalar<> numInsts;
180
181 void countInst()
182 {
183 numInst++;
184 numInsts++;
185
186 thread->funcExeInst++;
187 }
188
189 virtual Counter totalInstructions() const
190 {
191 return numInst - startNumInst;
192 }
193
194 // Mask to align PCs to MachInst sized boundaries
195 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
196
197 // number of simulated memory references
198 Stats::Scalar<> numMemRefs;
199
200 // number of simulated loads
201 Counter numLoad;
202 Counter startNumLoad;
203
204 // number of idle cycles
205 Stats::Average<> notIdleFraction;
206 Stats::Formula idleFraction;
207
208 // number of cycles stalled for I-cache responses
209 Stats::Scalar<> icacheStallCycles;
210 Counter lastIcacheStall;
211
212 // number of cycles stalled for I-cache retries
213 Stats::Scalar<> icacheRetryCycles;
214 Counter lastIcacheRetry;
215
216 // number of cycles stalled for D-cache responses
217 Stats::Scalar<> dcacheStallCycles;
218 Counter lastDcacheStall;
219
220 // number of cycles stalled for D-cache retries
221 Stats::Scalar<> dcacheRetryCycles;
222 Counter lastDcacheRetry;
223
224 virtual void serialize(std::ostream &os);
225 virtual void unserialize(Checkpoint *cp, const std::string §ion);
226
227 // These functions are only used in CPU models that split
228 // effective address computation from the actual memory access.
229 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
| 1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Dave Greene
30 * Nathan Binkert
31 */
32
33#ifndef __CPU_SIMPLE_BASE_HH__
34#define __CPU_SIMPLE_BASE_HH__
35
36#include "arch/predecoder.hh"
37#include "base/statistics.hh"
38#include "config/full_system.hh"
39#include "cpu/base.hh"
40#include "cpu/simple_thread.hh"
41#include "cpu/pc_event.hh"
42#include "cpu/static_inst.hh"
43#include "mem/packet.hh"
44#include "mem/port.hh"
45#include "mem/request.hh"
46#include "sim/eventq.hh"
47#include "sim/system.hh"
48
49// forward declarations
50#if FULL_SYSTEM
51class Processor;
52namespace TheISA
53{
54 class ITB;
55 class DTB;
56}
57class MemObject;
58
59#else
60
61class Process;
62
63#endif // FULL_SYSTEM
64
65class RemoteGDB;
66class GDBListener;
67
68namespace TheISA
69{
70 class Predecoder;
71}
72class ThreadContext;
73class Checkpoint;
74
75namespace Trace {
76 class InstRecord;
77}
78
79class BaseSimpleCPUParams;
80
81
82class BaseSimpleCPU : public BaseCPU
83{
84 protected:
85 typedef TheISA::MiscReg MiscReg;
86 typedef TheISA::FloatReg FloatReg;
87 typedef TheISA::FloatRegBits FloatRegBits;
88
89 protected:
90 Trace::InstRecord *traceData;
91
92 inline void checkPcEventQueue() {
93 Addr oldpc;
94 do {
95 oldpc = thread->readPC();
96 system->pcEventQueue.service(tc);
97 } while (oldpc != thread->readPC());
98 }
99
100 public:
101 void post_interrupt(int int_num, int index);
102
103 void zero_fill_64(Addr addr) {
104 static int warned = 0;
105 if (!warned) {
106 warn ("WH64 is not implemented");
107 warned = 1;
108 }
109 };
110
111 public:
112 BaseSimpleCPU(BaseSimpleCPUParams *params);
113 virtual ~BaseSimpleCPU();
114
115 public:
116 /** SimpleThread object, provides all the architectural state. */
117 SimpleThread *thread;
118
119 /** ThreadContext object, provides an interface for external
120 * objects to modify this thread's state.
121 */
122 ThreadContext *tc;
123 protected:
124 int cpuId;
125
126 enum Status {
127 Idle,
128 Running,
129 IcacheRetry,
130 IcacheWaitResponse,
131 IcacheWaitSwitch,
132 DcacheRetry,
133 DcacheWaitResponse,
134 DcacheWaitSwitch,
135 SwitchedOut
136 };
137
138 Status _status;
139
140 public:
141
142#if FULL_SYSTEM
143 Addr dbg_vtophys(Addr addr);
144
145 bool interval_stats;
146#endif
147
148 // current instruction
149 TheISA::MachInst inst;
150
151 // The predecoder
152 TheISA::Predecoder predecoder;
153
154 StaticInstPtr curStaticInst;
155 StaticInstPtr curMacroStaticInst;
156
157 //This is the offset from the current pc that fetch should be performed at
158 Addr fetchOffset;
159 //This flag says to stay at the current pc. This is useful for
160 //instructions which go beyond MachInst boundaries.
161 bool stayAtPC;
162
163 void checkForInterrupts();
164 Fault setupFetchRequest(Request *req);
165 void preExecute();
166 void postExecute();
167 void advancePC(Fault fault);
168
169 virtual void deallocateContext(int thread_num);
170 virtual void haltContext(int thread_num);
171
172 // statistics
173 virtual void regStats();
174 virtual void resetStats();
175
176 // number of simulated instructions
177 Counter numInst;
178 Counter startNumInst;
179 Stats::Scalar<> numInsts;
180
181 void countInst()
182 {
183 numInst++;
184 numInsts++;
185
186 thread->funcExeInst++;
187 }
188
189 virtual Counter totalInstructions() const
190 {
191 return numInst - startNumInst;
192 }
193
194 // Mask to align PCs to MachInst sized boundaries
195 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
196
197 // number of simulated memory references
198 Stats::Scalar<> numMemRefs;
199
200 // number of simulated loads
201 Counter numLoad;
202 Counter startNumLoad;
203
204 // number of idle cycles
205 Stats::Average<> notIdleFraction;
206 Stats::Formula idleFraction;
207
208 // number of cycles stalled for I-cache responses
209 Stats::Scalar<> icacheStallCycles;
210 Counter lastIcacheStall;
211
212 // number of cycles stalled for I-cache retries
213 Stats::Scalar<> icacheRetryCycles;
214 Counter lastIcacheRetry;
215
216 // number of cycles stalled for D-cache responses
217 Stats::Scalar<> dcacheStallCycles;
218 Counter lastDcacheStall;
219
220 // number of cycles stalled for D-cache retries
221 Stats::Scalar<> dcacheRetryCycles;
222 Counter lastDcacheRetry;
223
224 virtual void serialize(std::ostream &os);
225 virtual void unserialize(Checkpoint *cp, const std::string §ion);
226
227 // These functions are only used in CPU models that split
228 // effective address computation from the actual memory access.
229 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
|
231 M5_DUMMY_RETURN}
232
233 void prefetch(Addr addr, unsigned flags)
234 {
235 // need to do this...
236 }
237
238 void writeHint(Addr addr, int size, unsigned flags)
239 {
240 // need to do this...
241 }
242
243
244 Fault copySrcTranslate(Addr src);
245
246 Fault copy(Addr dest);
247
248 // The register accessor methods provide the index of the
249 // instruction's operand (e.g., 0 or 1), not the architectural
250 // register index, to simplify the implementation of register
251 // renaming. We find the architectural register index by indexing
252 // into the instruction's own operand index table. Note that a
253 // raw pointer to the StaticInst is provided instead of a
254 // ref-counted StaticInstPtr to redice overhead. This is fine as
255 // long as these methods don't copy the pointer into any long-term
256 // storage (which is pretty hard to imagine they would have reason
257 // to do).
258
259 uint64_t readIntRegOperand(const StaticInst *si, int idx)
260 {
261 return thread->readIntReg(si->srcRegIdx(idx));
262 }
263
264 FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
265 {
266 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
267 return thread->readFloatReg(reg_idx, width);
268 }
269
270 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
271 {
272 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
273 return thread->readFloatReg(reg_idx);
274 }
275
276 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
277 int width)
278 {
279 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
280 return thread->readFloatRegBits(reg_idx, width);
281 }
282
283 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
284 {
285 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
286 return thread->readFloatRegBits(reg_idx);
287 }
288
289 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
290 {
291 thread->setIntReg(si->destRegIdx(idx), val);
292 }
293
294 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
295 int width)
296 {
297 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
298 thread->setFloatReg(reg_idx, val, width);
299 }
300
301 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
302 {
303 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
304 thread->setFloatReg(reg_idx, val);
305 }
306
307 void setFloatRegOperandBits(const StaticInst *si, int idx,
308 FloatRegBits val, int width)
309 {
310 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
311 thread->setFloatRegBits(reg_idx, val, width);
312 }
313
314 void setFloatRegOperandBits(const StaticInst *si, int idx,
315 FloatRegBits val)
316 {
317 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
318 thread->setFloatRegBits(reg_idx, val);
319 }
320
321 uint64_t readPC() { return thread->readPC(); }
322 uint64_t readMicroPC() { return thread->readMicroPC(); }
323 uint64_t readNextPC() { return thread->readNextPC(); }
324 uint64_t readNextMicroPC() { return thread->readNextMicroPC(); }
325 uint64_t readNextNPC() { return thread->readNextNPC(); }
326
327 void setPC(uint64_t val) { thread->setPC(val); }
328 void setMicroPC(uint64_t val) { thread->setMicroPC(val); }
329 void setNextPC(uint64_t val) { thread->setNextPC(val); }
330 void setNextMicroPC(uint64_t val) { thread->setNextMicroPC(val); }
331 void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
332
333 MiscReg readMiscRegNoEffect(int misc_reg)
334 {
335 return thread->readMiscRegNoEffect(misc_reg);
336 }
337
338 MiscReg readMiscReg(int misc_reg)
339 {
340 return thread->readMiscReg(misc_reg);
341 }
342
343 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
344 {
345 return thread->setMiscRegNoEffect(misc_reg, val);
346 }
347
348 void setMiscReg(int misc_reg, const MiscReg &val)
349 {
350 return thread->setMiscReg(misc_reg, val);
351 }
352
353 MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
354 {
355 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
356 return thread->readMiscRegNoEffect(reg_idx);
357 }
358
359 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
360 {
361 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
362 return thread->readMiscReg(reg_idx);
363 }
364
365 void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val)
366 {
367 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
368 return thread->setMiscRegNoEffect(reg_idx, val);
369 }
370
371 void setMiscRegOperand(
372 const StaticInst *si, int idx, const MiscReg &val)
373 {
374 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
375 return thread->setMiscReg(reg_idx, val);
376 }
377
378 void demapPage(Addr vaddr, uint64_t asn)
379 {
380 thread->demapPage(vaddr, asn);
381 }
382
383 void demapInstPage(Addr vaddr, uint64_t asn)
384 {
385 thread->demapInstPage(vaddr, asn);
386 }
387
388 void demapDataPage(Addr vaddr, uint64_t asn)
389 {
390 thread->demapDataPage(vaddr, asn);
391 }
392
393 unsigned readStCondFailures() {
394 return thread->readStCondFailures();
395 }
396
397 void setStCondFailures(unsigned sc_failures) {
398 thread->setStCondFailures(sc_failures);
399 }
400
401 MiscReg readRegOtherThread(int regIdx, int tid = -1)
402 {
403 panic("Simple CPU models do not support multithreaded "
404 "register access.\n");
405 }
406
407 void setRegOtherThread(int regIdx, const MiscReg &val, int tid = -1)
408 {
409 panic("Simple CPU models do not support multithreaded "
410 "register access.\n");
411 }
412
413 //Fault CacheOp(uint8_t Op, Addr EA);
414
415#if FULL_SYSTEM
416 Fault hwrei() { return thread->hwrei(); }
417 void ev5_trap(Fault fault) { fault->invoke(tc); }
418 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
419#else
420 void syscall(int64_t callnum) { thread->syscall(callnum); }
421#endif
422
423 bool misspeculating() { return thread->misspeculating(); }
424 ThreadContext *tcBase() { return tc; }
425};
426
427#endif // __CPU_SIMPLE_BASE_HH__
| 231 M5_DUMMY_RETURN}
232
233 void prefetch(Addr addr, unsigned flags)
234 {
235 // need to do this...
236 }
237
238 void writeHint(Addr addr, int size, unsigned flags)
239 {
240 // need to do this...
241 }
242
243
244 Fault copySrcTranslate(Addr src);
245
246 Fault copy(Addr dest);
247
248 // The register accessor methods provide the index of the
249 // instruction's operand (e.g., 0 or 1), not the architectural
250 // register index, to simplify the implementation of register
251 // renaming. We find the architectural register index by indexing
252 // into the instruction's own operand index table. Note that a
253 // raw pointer to the StaticInst is provided instead of a
254 // ref-counted StaticInstPtr to redice overhead. This is fine as
255 // long as these methods don't copy the pointer into any long-term
256 // storage (which is pretty hard to imagine they would have reason
257 // to do).
258
259 uint64_t readIntRegOperand(const StaticInst *si, int idx)
260 {
261 return thread->readIntReg(si->srcRegIdx(idx));
262 }
263
264 FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
265 {
266 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
267 return thread->readFloatReg(reg_idx, width);
268 }
269
270 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
271 {
272 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
273 return thread->readFloatReg(reg_idx);
274 }
275
276 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
277 int width)
278 {
279 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
280 return thread->readFloatRegBits(reg_idx, width);
281 }
282
283 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
284 {
285 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
286 return thread->readFloatRegBits(reg_idx);
287 }
288
289 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
290 {
291 thread->setIntReg(si->destRegIdx(idx), val);
292 }
293
294 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
295 int width)
296 {
297 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
298 thread->setFloatReg(reg_idx, val, width);
299 }
300
301 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
302 {
303 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
304 thread->setFloatReg(reg_idx, val);
305 }
306
307 void setFloatRegOperandBits(const StaticInst *si, int idx,
308 FloatRegBits val, int width)
309 {
310 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
311 thread->setFloatRegBits(reg_idx, val, width);
312 }
313
314 void setFloatRegOperandBits(const StaticInst *si, int idx,
315 FloatRegBits val)
316 {
317 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
318 thread->setFloatRegBits(reg_idx, val);
319 }
320
321 uint64_t readPC() { return thread->readPC(); }
322 uint64_t readMicroPC() { return thread->readMicroPC(); }
323 uint64_t readNextPC() { return thread->readNextPC(); }
324 uint64_t readNextMicroPC() { return thread->readNextMicroPC(); }
325 uint64_t readNextNPC() { return thread->readNextNPC(); }
326
327 void setPC(uint64_t val) { thread->setPC(val); }
328 void setMicroPC(uint64_t val) { thread->setMicroPC(val); }
329 void setNextPC(uint64_t val) { thread->setNextPC(val); }
330 void setNextMicroPC(uint64_t val) { thread->setNextMicroPC(val); }
331 void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
332
333 MiscReg readMiscRegNoEffect(int misc_reg)
334 {
335 return thread->readMiscRegNoEffect(misc_reg);
336 }
337
338 MiscReg readMiscReg(int misc_reg)
339 {
340 return thread->readMiscReg(misc_reg);
341 }
342
343 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
344 {
345 return thread->setMiscRegNoEffect(misc_reg, val);
346 }
347
348 void setMiscReg(int misc_reg, const MiscReg &val)
349 {
350 return thread->setMiscReg(misc_reg, val);
351 }
352
353 MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
354 {
355 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
356 return thread->readMiscRegNoEffect(reg_idx);
357 }
358
359 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
360 {
361 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
362 return thread->readMiscReg(reg_idx);
363 }
364
365 void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val)
366 {
367 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
368 return thread->setMiscRegNoEffect(reg_idx, val);
369 }
370
371 void setMiscRegOperand(
372 const StaticInst *si, int idx, const MiscReg &val)
373 {
374 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
375 return thread->setMiscReg(reg_idx, val);
376 }
377
378 void demapPage(Addr vaddr, uint64_t asn)
379 {
380 thread->demapPage(vaddr, asn);
381 }
382
383 void demapInstPage(Addr vaddr, uint64_t asn)
384 {
385 thread->demapInstPage(vaddr, asn);
386 }
387
388 void demapDataPage(Addr vaddr, uint64_t asn)
389 {
390 thread->demapDataPage(vaddr, asn);
391 }
392
393 unsigned readStCondFailures() {
394 return thread->readStCondFailures();
395 }
396
397 void setStCondFailures(unsigned sc_failures) {
398 thread->setStCondFailures(sc_failures);
399 }
400
401 MiscReg readRegOtherThread(int regIdx, int tid = -1)
402 {
403 panic("Simple CPU models do not support multithreaded "
404 "register access.\n");
405 }
406
407 void setRegOtherThread(int regIdx, const MiscReg &val, int tid = -1)
408 {
409 panic("Simple CPU models do not support multithreaded "
410 "register access.\n");
411 }
412
413 //Fault CacheOp(uint8_t Op, Addr EA);
414
415#if FULL_SYSTEM
416 Fault hwrei() { return thread->hwrei(); }
417 void ev5_trap(Fault fault) { fault->invoke(tc); }
418 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
419#else
420 void syscall(int64_t callnum) { thread->syscall(callnum); }
421#endif
422
423 bool misspeculating() { return thread->misspeculating(); }
424 ThreadContext *tcBase() { return tc; }
425};
426
427#endif // __CPU_SIMPLE_BASE_HH__
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