1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Dave Greene
30 * Nathan Binkert
31 */
32
33#ifndef __CPU_SIMPLE_BASE_HH__
34#define __CPU_SIMPLE_BASE_HH__
35
36#include "arch/predecoder.hh"
37#include "base/statistics.hh"
38#include "config/full_system.hh"
39#include "cpu/base.hh"
40#include "cpu/simple_thread.hh"
41#include "cpu/pc_event.hh"
42#include "cpu/static_inst.hh"
43#include "mem/packet.hh"
44#include "mem/port.hh"
45#include "mem/request.hh"
46#include "sim/eventq.hh"
47
48// forward declarations
49#if FULL_SYSTEM
50class Processor;
51namespace TheISA
52{
53 class ITB;
54 class DTB;
55}
56class MemObject;
57
58#else
59
60class Process;
61
62#endif // FULL_SYSTEM
63
64class RemoteGDB;
65class GDBListener;
66
67namespace TheISA
68{
69 class Predecoder;
70}
71class ThreadContext;
72class Checkpoint;
73
74namespace Trace {
75 class InstRecord;
76}
77
78
79class BaseSimpleCPU : public BaseCPU
80{
81 protected:
82 typedef TheISA::MiscReg MiscReg;
83 typedef TheISA::FloatReg FloatReg;
84 typedef TheISA::FloatRegBits FloatRegBits;
85
86 protected:
87 Trace::InstRecord *traceData;
88
89 public:
90 void post_interrupt(int int_num, int index);
91
92 void zero_fill_64(Addr addr) {
93 static int warned = 0;
94 if (!warned) {
95 warn ("WH64 is not implemented");
96 warned = 1;
97 }
98 };
99
100 public:
101 struct Params : public BaseCPU::Params
102 {
103 TheISA::ITB *itb;
104 TheISA::DTB *dtb;
105#if !FULL_SYSTEM
106 Process *process;
107#endif
108 };
109 BaseSimpleCPU(Params *params);
110 virtual ~BaseSimpleCPU();
111
112 public:
113 /** SimpleThread object, provides all the architectural state. */
114 SimpleThread *thread;
115
116 /** ThreadContext object, provides an interface for external
117 * objects to modify this thread's state.
118 */
119 ThreadContext *tc;
120 protected:
121 int cpuId;
122
123 public:
124
125#if FULL_SYSTEM
126 Addr dbg_vtophys(Addr addr);
127
128 bool interval_stats;
129#endif
130
131 // current instruction
132 TheISA::MachInst inst;
133
134 // The predecoder
135 TheISA::Predecoder predecoder;
136
137 StaticInstPtr curStaticInst;
138 StaticInstPtr curMacroStaticInst;
139
140 //This is the offset from the current pc that fetch should be performed at
141 Addr fetchOffset;
142 //This flag says to stay at the current pc. This is useful for
143 //instructions which go beyond MachInst boundaries.
144 bool stayAtPC;
145
146 void checkForInterrupts();
147 Fault setupFetchRequest(Request *req);
148 void preExecute();
149 void postExecute();
150 void advancePC(Fault fault);
151
152 virtual void deallocateContext(int thread_num);
153 virtual void haltContext(int thread_num);
154
155 // statistics
156 virtual void regStats();
157 virtual void resetStats();
158
159 // number of simulated instructions
160 Counter numInst;
161 Counter startNumInst;
162 Stats::Scalar<> numInsts;
163
164 void countInst()
165 {
166 numInst++;
167 numInsts++;
168
169 thread->funcExeInst++;
170 }
171
172 virtual Counter totalInstructions() const
173 {
174 return numInst - startNumInst;
175 }
176
177 // Mask to align PCs to MachInst sized boundaries
178 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
179
180 // number of simulated memory references
181 Stats::Scalar<> numMemRefs;
182
183 // number of simulated loads
184 Counter numLoad;
185 Counter startNumLoad;
186
187 // number of idle cycles
188 Stats::Average<> notIdleFraction;
189 Stats::Formula idleFraction;
190
191 // number of cycles stalled for I-cache responses
192 Stats::Scalar<> icacheStallCycles;
193 Counter lastIcacheStall;
194
195 // number of cycles stalled for I-cache retries
196 Stats::Scalar<> icacheRetryCycles;
197 Counter lastIcacheRetry;
198
199 // number of cycles stalled for D-cache responses
200 Stats::Scalar<> dcacheStallCycles;
201 Counter lastDcacheStall;
202
203 // number of cycles stalled for D-cache retries
204 Stats::Scalar<> dcacheRetryCycles;
205 Counter lastDcacheRetry;
206
207 virtual void serialize(std::ostream &os);
208 virtual void unserialize(Checkpoint *cp, const std::string §ion);
209
210 // These functions are only used in CPU models that split
211 // effective address computation from the actual memory access.
212 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
213 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n");
214 M5_DUMMY_RETURN}
215
216 void prefetch(Addr addr, unsigned flags)
217 {
218 // need to do this...
219 }
220
221 void writeHint(Addr addr, int size, unsigned flags)
222 {
223 // need to do this...
224 }
225
226
227 Fault copySrcTranslate(Addr src);
228
229 Fault copy(Addr dest);
230
231 // The register accessor methods provide the index of the
232 // instruction's operand (e.g., 0 or 1), not the architectural
233 // register index, to simplify the implementation of register
234 // renaming. We find the architectural register index by indexing
235 // into the instruction's own operand index table. Note that a
236 // raw pointer to the StaticInst is provided instead of a
237 // ref-counted StaticInstPtr to redice overhead. This is fine as
238 // long as these methods don't copy the pointer into any long-term
239 // storage (which is pretty hard to imagine they would have reason
240 // to do).
241
242 uint64_t readIntRegOperand(const StaticInst *si, int idx)
243 {
244 return thread->readIntReg(si->srcRegIdx(idx));
245 }
246
247 FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
248 {
249 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
250 return thread->readFloatReg(reg_idx, width);
251 }
252
253 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
254 {
255 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
256 return thread->readFloatReg(reg_idx);
257 }
258
259 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
260 int width)
261 {
262 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
263 return thread->readFloatRegBits(reg_idx, width);
264 }
265
266 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
267 {
268 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
269 return thread->readFloatRegBits(reg_idx);
270 }
271
272 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
273 {
274 thread->setIntReg(si->destRegIdx(idx), val);
275 }
276
277 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
278 int width)
279 {
280 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
281 thread->setFloatReg(reg_idx, val, width);
282 }
283
284 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
285 {
286 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
287 thread->setFloatReg(reg_idx, val);
288 }
289
290 void setFloatRegOperandBits(const StaticInst *si, int idx,
291 FloatRegBits val, int width)
292 {
293 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
294 thread->setFloatRegBits(reg_idx, val, width);
295 }
296
297 void setFloatRegOperandBits(const StaticInst *si, int idx,
298 FloatRegBits val)
299 {
300 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
301 thread->setFloatRegBits(reg_idx, val);
302 }
303
304 uint64_t readPC() { return thread->readPC(); }
305 uint64_t readMicroPC() { return thread->readMicroPC(); }
306 uint64_t readNextPC() { return thread->readNextPC(); }
307 uint64_t readNextMicroPC() { return thread->readNextMicroPC(); }
308 uint64_t readNextNPC() { return thread->readNextNPC(); }
309
310 void setPC(uint64_t val) { thread->setPC(val); }
311 void setMicroPC(uint64_t val) { thread->setMicroPC(val); }
312 void setNextPC(uint64_t val) { thread->setNextPC(val); }
313 void setNextMicroPC(uint64_t val) { thread->setNextMicroPC(val); }
314 void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
315
316 MiscReg readMiscRegNoEffect(int misc_reg)
317 {
318 return thread->readMiscRegNoEffect(misc_reg);
319 }
320
321 MiscReg readMiscReg(int misc_reg)
322 {
323 return thread->readMiscReg(misc_reg);
324 }
325
326 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
327 {
328 return thread->setMiscRegNoEffect(misc_reg, val);
329 }
330
331 void setMiscReg(int misc_reg, const MiscReg &val)
332 {
333 return thread->setMiscReg(misc_reg, val);
334 }
335
336 MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
337 {
338 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
339 return thread->readMiscRegNoEffect(reg_idx);
340 }
341
342 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
343 {
344 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
345 return thread->readMiscReg(reg_idx);
346 }
347
348 void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val)
349 {
350 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
351 return thread->setMiscRegNoEffect(reg_idx, val);
352 }
353
354 void setMiscRegOperand(
355 const StaticInst *si, int idx, const MiscReg &val)
356 {
357 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
358 return thread->setMiscReg(reg_idx, val);
359 }
360
361 unsigned readStCondFailures() {
362 return thread->readStCondFailures();
363 }
364
365 void setStCondFailures(unsigned sc_failures) {
366 thread->setStCondFailures(sc_failures);
367 }
368
369 MiscReg readRegOtherThread(int regIdx, int tid = -1)
370 {
371 panic("Simple CPU models do not support multithreaded "
372 "register access.\n");
373 }
374
375 void setRegOtherThread(int regIdx, const MiscReg &val, int tid = -1)
376 {
377 panic("Simple CPU models do not support multithreaded "
378 "register access.\n");
379 }
380
| 1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 * Dave Greene
30 * Nathan Binkert
31 */
32
33#ifndef __CPU_SIMPLE_BASE_HH__
34#define __CPU_SIMPLE_BASE_HH__
35
36#include "arch/predecoder.hh"
37#include "base/statistics.hh"
38#include "config/full_system.hh"
39#include "cpu/base.hh"
40#include "cpu/simple_thread.hh"
41#include "cpu/pc_event.hh"
42#include "cpu/static_inst.hh"
43#include "mem/packet.hh"
44#include "mem/port.hh"
45#include "mem/request.hh"
46#include "sim/eventq.hh"
47
48// forward declarations
49#if FULL_SYSTEM
50class Processor;
51namespace TheISA
52{
53 class ITB;
54 class DTB;
55}
56class MemObject;
57
58#else
59
60class Process;
61
62#endif // FULL_SYSTEM
63
64class RemoteGDB;
65class GDBListener;
66
67namespace TheISA
68{
69 class Predecoder;
70}
71class ThreadContext;
72class Checkpoint;
73
74namespace Trace {
75 class InstRecord;
76}
77
78
79class BaseSimpleCPU : public BaseCPU
80{
81 protected:
82 typedef TheISA::MiscReg MiscReg;
83 typedef TheISA::FloatReg FloatReg;
84 typedef TheISA::FloatRegBits FloatRegBits;
85
86 protected:
87 Trace::InstRecord *traceData;
88
89 public:
90 void post_interrupt(int int_num, int index);
91
92 void zero_fill_64(Addr addr) {
93 static int warned = 0;
94 if (!warned) {
95 warn ("WH64 is not implemented");
96 warned = 1;
97 }
98 };
99
100 public:
101 struct Params : public BaseCPU::Params
102 {
103 TheISA::ITB *itb;
104 TheISA::DTB *dtb;
105#if !FULL_SYSTEM
106 Process *process;
107#endif
108 };
109 BaseSimpleCPU(Params *params);
110 virtual ~BaseSimpleCPU();
111
112 public:
113 /** SimpleThread object, provides all the architectural state. */
114 SimpleThread *thread;
115
116 /** ThreadContext object, provides an interface for external
117 * objects to modify this thread's state.
118 */
119 ThreadContext *tc;
120 protected:
121 int cpuId;
122
123 public:
124
125#if FULL_SYSTEM
126 Addr dbg_vtophys(Addr addr);
127
128 bool interval_stats;
129#endif
130
131 // current instruction
132 TheISA::MachInst inst;
133
134 // The predecoder
135 TheISA::Predecoder predecoder;
136
137 StaticInstPtr curStaticInst;
138 StaticInstPtr curMacroStaticInst;
139
140 //This is the offset from the current pc that fetch should be performed at
141 Addr fetchOffset;
142 //This flag says to stay at the current pc. This is useful for
143 //instructions which go beyond MachInst boundaries.
144 bool stayAtPC;
145
146 void checkForInterrupts();
147 Fault setupFetchRequest(Request *req);
148 void preExecute();
149 void postExecute();
150 void advancePC(Fault fault);
151
152 virtual void deallocateContext(int thread_num);
153 virtual void haltContext(int thread_num);
154
155 // statistics
156 virtual void regStats();
157 virtual void resetStats();
158
159 // number of simulated instructions
160 Counter numInst;
161 Counter startNumInst;
162 Stats::Scalar<> numInsts;
163
164 void countInst()
165 {
166 numInst++;
167 numInsts++;
168
169 thread->funcExeInst++;
170 }
171
172 virtual Counter totalInstructions() const
173 {
174 return numInst - startNumInst;
175 }
176
177 // Mask to align PCs to MachInst sized boundaries
178 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
179
180 // number of simulated memory references
181 Stats::Scalar<> numMemRefs;
182
183 // number of simulated loads
184 Counter numLoad;
185 Counter startNumLoad;
186
187 // number of idle cycles
188 Stats::Average<> notIdleFraction;
189 Stats::Formula idleFraction;
190
191 // number of cycles stalled for I-cache responses
192 Stats::Scalar<> icacheStallCycles;
193 Counter lastIcacheStall;
194
195 // number of cycles stalled for I-cache retries
196 Stats::Scalar<> icacheRetryCycles;
197 Counter lastIcacheRetry;
198
199 // number of cycles stalled for D-cache responses
200 Stats::Scalar<> dcacheStallCycles;
201 Counter lastDcacheStall;
202
203 // number of cycles stalled for D-cache retries
204 Stats::Scalar<> dcacheRetryCycles;
205 Counter lastDcacheRetry;
206
207 virtual void serialize(std::ostream &os);
208 virtual void unserialize(Checkpoint *cp, const std::string §ion);
209
210 // These functions are only used in CPU models that split
211 // effective address computation from the actual memory access.
212 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
213 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n");
214 M5_DUMMY_RETURN}
215
216 void prefetch(Addr addr, unsigned flags)
217 {
218 // need to do this...
219 }
220
221 void writeHint(Addr addr, int size, unsigned flags)
222 {
223 // need to do this...
224 }
225
226
227 Fault copySrcTranslate(Addr src);
228
229 Fault copy(Addr dest);
230
231 // The register accessor methods provide the index of the
232 // instruction's operand (e.g., 0 or 1), not the architectural
233 // register index, to simplify the implementation of register
234 // renaming. We find the architectural register index by indexing
235 // into the instruction's own operand index table. Note that a
236 // raw pointer to the StaticInst is provided instead of a
237 // ref-counted StaticInstPtr to redice overhead. This is fine as
238 // long as these methods don't copy the pointer into any long-term
239 // storage (which is pretty hard to imagine they would have reason
240 // to do).
241
242 uint64_t readIntRegOperand(const StaticInst *si, int idx)
243 {
244 return thread->readIntReg(si->srcRegIdx(idx));
245 }
246
247 FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
248 {
249 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
250 return thread->readFloatReg(reg_idx, width);
251 }
252
253 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
254 {
255 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
256 return thread->readFloatReg(reg_idx);
257 }
258
259 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
260 int width)
261 {
262 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
263 return thread->readFloatRegBits(reg_idx, width);
264 }
265
266 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
267 {
268 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
269 return thread->readFloatRegBits(reg_idx);
270 }
271
272 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
273 {
274 thread->setIntReg(si->destRegIdx(idx), val);
275 }
276
277 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
278 int width)
279 {
280 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
281 thread->setFloatReg(reg_idx, val, width);
282 }
283
284 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
285 {
286 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
287 thread->setFloatReg(reg_idx, val);
288 }
289
290 void setFloatRegOperandBits(const StaticInst *si, int idx,
291 FloatRegBits val, int width)
292 {
293 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
294 thread->setFloatRegBits(reg_idx, val, width);
295 }
296
297 void setFloatRegOperandBits(const StaticInst *si, int idx,
298 FloatRegBits val)
299 {
300 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
301 thread->setFloatRegBits(reg_idx, val);
302 }
303
304 uint64_t readPC() { return thread->readPC(); }
305 uint64_t readMicroPC() { return thread->readMicroPC(); }
306 uint64_t readNextPC() { return thread->readNextPC(); }
307 uint64_t readNextMicroPC() { return thread->readNextMicroPC(); }
308 uint64_t readNextNPC() { return thread->readNextNPC(); }
309
310 void setPC(uint64_t val) { thread->setPC(val); }
311 void setMicroPC(uint64_t val) { thread->setMicroPC(val); }
312 void setNextPC(uint64_t val) { thread->setNextPC(val); }
313 void setNextMicroPC(uint64_t val) { thread->setNextMicroPC(val); }
314 void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
315
316 MiscReg readMiscRegNoEffect(int misc_reg)
317 {
318 return thread->readMiscRegNoEffect(misc_reg);
319 }
320
321 MiscReg readMiscReg(int misc_reg)
322 {
323 return thread->readMiscReg(misc_reg);
324 }
325
326 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
327 {
328 return thread->setMiscRegNoEffect(misc_reg, val);
329 }
330
331 void setMiscReg(int misc_reg, const MiscReg &val)
332 {
333 return thread->setMiscReg(misc_reg, val);
334 }
335
336 MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
337 {
338 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
339 return thread->readMiscRegNoEffect(reg_idx);
340 }
341
342 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
343 {
344 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
345 return thread->readMiscReg(reg_idx);
346 }
347
348 void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val)
349 {
350 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
351 return thread->setMiscRegNoEffect(reg_idx, val);
352 }
353
354 void setMiscRegOperand(
355 const StaticInst *si, int idx, const MiscReg &val)
356 {
357 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
358 return thread->setMiscReg(reg_idx, val);
359 }
360
361 unsigned readStCondFailures() {
362 return thread->readStCondFailures();
363 }
364
365 void setStCondFailures(unsigned sc_failures) {
366 thread->setStCondFailures(sc_failures);
367 }
368
369 MiscReg readRegOtherThread(int regIdx, int tid = -1)
370 {
371 panic("Simple CPU models do not support multithreaded "
372 "register access.\n");
373 }
374
375 void setRegOtherThread(int regIdx, const MiscReg &val, int tid = -1)
376 {
377 panic("Simple CPU models do not support multithreaded "
378 "register access.\n");
379 }
380
|